Altera PHY IP Core manuals

Altera PHY IP Core User's Guide (176 pages)

Brand: Altera | Category: Memory modules | Size: 3.19 MB |

English

Table of contents

User Guide

1

Contents

3

Chapter 8. Latency

5

Chapter 9. Timing Diagrams

5

1. About This IP

7

Release Information

8

Device Family Support

8

1–4 Chapter 1: About This IP

10

Features

10

ALTMEMPHY Megafunction

11

Note to Table 1–4:

12

Note to Table 1–5:

12

High-Performance Controller

13

System Requirements

14

Installation and Licensing

14

Free Evaluation

15

1–10 Chapter 1: About This IP

16

2. Getting Started

17

Specifying Parameters

18

SOPC Builder Flow

19

Generated Files

22

3. Parameter Settings

29

Memory Settings

30

ALTMEMPHY Parameter Settings

31

Note to Table 3–3:

34

Note to Table 3–5:

38

PHY Settings

39

Board Settings

41

Controller Settings

42

4. Compiling and Simulating

47

Compiling the Design

48

Simulating the Design

50

Calibration

55

DDR3 SDRAM Without Leveling

55

Step 6: Postamble

57

Step 7: Prepare for User Mode

57

DDR3 SDRAM With Leveling

59

Step 2: Write Leveling

62

Address and Command Datapath

63

° ), or the inverted

64

Clock and Reset Management

65

Clock Management

65

Note to Table 5–1:

67

Reset Management

69

Read Datapath

70

Write Datapath

74

ALTMEMPHY Signals

75

Notes to Table 5–3:

77

Note to Table 5–3:

79

Notes to Table 5–5:

82

PHY-to-Controller Interfaces

83

Notes to Figure 5–17:

86

Notes to Figure 5–18:

87

Notes to Figure 5–19:

88

Notes to Figure 5–20:

89

Preliminary Steps

90

Design Considerations

90

Clocks and Resets

90

Using a Custom Controller

91

6. Functional Description—

95

Command FIFO Buffer

96

PHY Interface Logic

98

Control Logic

99

Figure 6–3. ECC Block Diagram

100

Block Description

101

Interrupts

102

Partial Writes

102

Partial Bursts

103

ECC Latency

103

ECC Registers

104

ECC Register Bits

106

Example Top-Level File

108

Example Driver

109

Top-level Signals Description

110

or vhd file

111

Note to Table 6–14:

114

7. Functional Description—

117

Write Data FIFO Buffer

120

Command Queue

120

Bank Management Logic

120

Timer Logic

121

Command-Issuing State Machine

121

ODT Generation Logic

122

User-Refresh Commands

122

Multi-Cast Write

122

Low-Power Mode Logic

123

Error Correction Coding (ECC)

123

Notes to Table 7–7:

133

Register Maps Description

134

ALTMEMPHY Register Map

135

Controller Register Map

137

8. Latency

143

8–2 Chapter 8: Latency

144

Chapter 8: Latency 8–3

145

8–4 Chapter 8: Latency

146

9. Timing Diagrams

147

Auto-Precharge

148

[1] [2] [3]

148

User Refresh

149

Initialization Timing

156

Calibration Timing

158

AABBCCDD AABBCCDD AABBCCDD

162

EEFF0011 EEFF0011 EEFF0011

162

[1] [3] [4][2]

166

Half-Rate Read With Gaps

168

Half-Rate Write With Gaps

169

[2][1] [5] [4] [6][3]

170

[12][6][7][10] [11]

172

Additional Information

175

Typographic Conventions

176

Altera devices