Altera FIR Compiler User Manual download pdf (Page 39)

Chapter 3: Parameter Settings 3–15

Specify the Architecture Specification

1. For this tutorial, select Distributed Arithmetic: Fully Parallel Filter structure with

a pipeline level of 3.

Although these settings create a filter that uses a large number of logic cells,

increasing the pipeline level to 3 decreases the number of clock cycles to one,

thereby greatly increasing system performance. These settings are shown in

Figure 3–9.

2. Click Finish when you have set the architecture parameters.

Figure 3–9. Specify the Filter Architecture

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Altera FIR Compiler User Manual Page 39