Altera ALTPLL (Phase-Locked Loop) IP Core User Manual Page 54
- Page / 69
- Table of contents
- BOOKMARKS
- ALTPLL Features 1
- Types of PLLs 2
- Operation Modes 3
- Expanding the PLL Lock Range 6
- ValueOption 7
- Output Clocks 9
- Altera Corporation 10
- Send Feedback 10
- Parameter Settings 10
- Summary of PLL Output Clocks 11
- Advanced Features 12
- 2014.08.18 13
- Clock Switchover 14
- Spread-Spectrum Clocking 17
- Gated Lock and Self-Reset 18
- Related Information 19
- Programmable Bandwidth 20
- Advanced PLL Parameters 22
- PLL Dynamic Reconfiguration 23
- DescriptionOption 24
- Dynamic Phase Configuration 26
- PLL Output Counter Cascading 28
- Using the Parameter Editor 30
- Legacy parameter 32
- 3. Ignore this directory 33
- Upgrading IP Cores 34
- Ports and Parameters 38
- DescriptionConditionPort Name 39
- ALTPLL Output Ports 41
- ALTPLL Bidirectional Port 46
- ALTPLL Parameters 46
- DescriptionTypeParameter 47
- StringOPERATION_MODE 54
- Design Examples 61
- -Altera Software 64
- Document Revision History 68
- Changes MadeVersionDate 69
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