Altera Stratix III User Manual download pdf (Page 22)

5–4 Chapter 5: Power Measurement

Measuring Power

Stratix III Development Kit User Guide © August 2008 Altera Corporation

5. Using the user input push buttons (Table 5–1 on page 5–1), advance through the

power states in Table 5–2 and Table 5–3 on page 5–2. Notice how power increases

as frequency and resources increase.

6. Press the User_PB3 button to enable the output pins on the HSMC connectors J8

and J18. LED7 (E19), signal o_noutput_ena_state, lights to indicate that the

outputs are enabled and toggling. Enabling the outputs further increases power

for each resource utilization percentage used by the Stratix III FPGA.

7. Press the User_PB3 button again to disable the outputs. LED7 turns off.

8. Set the POWER SELECT rotary switch SW6 to 7.

9. Repeat steps 4 through 7 to observe the I/O output power in watts on bank 2.

The sum of power results from the two sets of I/O banks provides the total FPGA I/O

power.

f For specific information about on-board measurements and the POWER SELECT

rotary switch, refer to the Stratix III Development Board Reference Manual.

Measuring Voltage with a DMM

To obtain power values by using a DMM, measure voltage across the sense-resistors,

R215, R218, and R214 on the board, then use the voltage measurements to calculate

power.

1 For best results, use a DMM with six-digit or greater accuracy.

FPGA I/O power is distributed by banks (Table 5–5), for which the sense resistors are

components R218 and R214. For the I/O power calculation, use the sum of voltage

measurements across these resistors while outputs are enabled. For the FPGA core

power calculation, measure the sense resistor voltage across R215.

Calculating Power

To obtain the power P in watts, measure the voltage across the sense resistors, V

SENSE

and calculate the nominal power as follows:

SENSE

= Voltage measured across the sense resistor

SENSE

= Current through the sense resistor

SUPPLY

= FPGA supply voltage

SENSE

= Sense resistor value in Table 5–5.

Table 5–5. Sense Resistors

FPGA Power Voltage

Sense

Resistor

Value

I/O Bank 2 2.5 V R214 0.009 Ω

Banks 4, 5 and 6 2.5 V R218 0.009 Ω

Core: VCCL 1.1 V R215 0.009 Ω

1 2 ... 17 18 19 20 21 22 23 24 25 26 27 ... 33 34

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