Altera Arria V GT FPGA User Manual download pdf (Page 38)

6–16 Chapter 6: Board Test System

Using the Board Test System

Arria V GT FPGA Development Kit November 2012 Altera Corporation

User Guide

Port (FPGA2)

The Port (FPGA2) control allows you to specify which interface to test. The following

port tests are available:

■ XCVR x4 (HSMB design run at 6.4 Gbps)

■ CMOS x3 (HSMB design run at 25 Mbps)

■ FMC XCVR x4 (FMC design run at 6.4 Gbps)

■ FMC CMOS x80 (FMC design run at 25 Mbps)

PMA Setting

The PMA Setting button allows you to make changes to the PMA parameters that

affect the active transceiver interface. The following settings are available for analysis:

■ Serial Loopback—Routes signals between the receiver and the transmitter. Enter

the following values to enable the serial loopbacks:

= high speed serial transceiver signals to loopback on the board

= serial loopback

= reverse serial loopback pre-CDR

= reverse serial loopback post-CDR

■ VOD—Specifies the voltage output differential of the transmitter buffer.

■ Pre-emphasis tap

■ Pre—Specifies the amount of pre-emphasis on the pre-tap of the transmitter

buffer.

■ First post—Specifies the amount of pre-emphasis on the first post tap of the

transmitter buffer.

■ Second post—Specifies the amount of pre-emphasis on the second post tap of

the transmitter buffer.

■ Equalizer—Specifies the setting for the receiver equalizer.

■ DC gain—Specifies the DC portion of the receiver equalizer.

Data Type

The Data type control specifies the type of data contained in transceiver transactions.

The following data types are available for transceiver analysis:

■ PRBS7—Selects pseudo-random 7-bit sequences.

■ PRBS15—Selects pseudo-random 15-bit sequences.

■ PRBS23—Selects pseudo-random 23-bit sequences.

■ PRBS31—Selects pseudo-random 31-bit sequences.

■ HF1—highest frequency divide-by-2 data pattern 10101010.

■ HF2—next highest frequency divide-by-4 data pattern 1100110011001100.

■ HF3—second lowest frequency divide-by-8 data pattern 1111000011110000.

■ LF FMC—lowest frequency divide-by-40 data pattern.

1 2 ... 33 34 35 36 37 38 39 40 41 42 43 ... 57 58

No comments

Altera Arria V GT FPGA User Manual Page 38