Altera Arria V GT FPGA User Manual download pdf (Page 37)

Chapter 6: Board Test System 6–15

Using the Board Test System

November 2012 Altera Corporation Arria V GT FPGA Development Kit

User Guide

The HSMB/FMC Tab

The HSMB/FMC tab (Figure 6–7) allows you to perform loopback tests on the XCVR

and CMOS ports.

1 You must have the loopback HSMB installed on the HSMC Port B connector that you

are testing for this test to work correctly.

The following sections describe the controls on the HSMB/FMC tab.

Status

The Status control displays the following status information during the loopback test:

■ PLL lock—Shows the PLL locked or unlocked state.

■ Channel lock—Shows the channel locked or unlocked state. When locked, all

lanes are word aligned and channel bonded.

■ Pattern sync—Shows the pattern synced or not synced state. The pattern is

considered synced when the start of the data sequence is detected.

Figure 6–7. The HSMB/FMC Tab

1 2 ... 32 33 34 35 36 37 38 39 40 41 42 ... 57 58

No comments

Altera Arria V GT FPGA User Manual Page 37