Altera Nios Ethernet manuals

Altera Nios Ethernet User Manual (22 pages)

Brand: Altera | Category: PC/workstation barebones | Size: 1.77 MB |

English

Table of contents

A. FPGA Basics Manuals

1

A.2. Hello-World SoC

3

Figure 7: BSP creation wizard

6

Figure 11: New ﬁle wizard

8

A.3. Self-Booting

13

Listing 3: Pin Assignment

16

Figure 26: Pin options

17

Figure 27: Pin options

18

Figure 28: Pin options

18

A.3.2. Writing the EPCS ﬂash

20

Altera Nios Ethernet User's Guide (89 pages)

Brand: Altera | Category: PC/workstation barebones | Size: 6.30 MB |

English

Table of contents

IFI Nios

1

II GMACII

1

IFI GMACII

2

Contents

4

Overview

5

Brief Description

6

Measurement

7

Block Diagram

9

IFI GMACII Implementation

11

OpenCore Plus Feature

12

IFI GMACII Reference Design

13

IFI GMACII Pricing

16

IFI GMACII Verification

17

Contacting Technical Support

18

© 2004 Altera Corporation

19

− Windows

20

− Solaris & Linux

20

Licensing

22

Set Up Licensing

23

Prerequisites

24

 Step 1: Generate

26

 Info + Documentation

28

 Parameters

28

 Information

28

Running a Reference Design

32

 GMACII_master is master for

34

 dpram_slave is mastered by

34

GMACII_master

34

Creating a Software Project

36

Syslib Settings

37

Run a Hardware Configuration

38

Your new HW Configuration

38

Your project

38

Port description

39

Necessary Assignments

41

Assumptions

42

Detailed Information

44

Define macros 1

50

Define macros 2

51

Define macros 3

52

Define macros 4

53

Define macros 5

54

Define macros 6

55

Define macros 7

56

Define macros 8

57

Base Address Offset FF8

58

Details DMA

59

Details transmitter

60

Filter Details MAC-ID

61

Filter Details MAC-IP

62

− IP which is divided in

63

 Open ifi_hello_gmacii.h

66

 Modify MAC ADDR

66

 Modify IP address

66

 Burst Destination MAC

67

 Burst Destination IP

67

Reference Software Flow

69

Timer controlled

70

Hardware Trigger controlled

71

Protocol Stack Fundamentals

72

UDP – User Datagram Protocol

77

 Reliable

80

 Flow control

80

 Also provides ports

80

Other protocols

81

What’s theoretical possible

82

Revision History

84

License Agreement

85

IFI Products and Services

89

Altera Nios Ethernet Specifications (36 pages)

Brand: Altera | Category: PC/workstation barebones | Size: 1.36 MB |

English

Table of contents

Tutorial

1

Contents

3

Introduction

5

Tutorial Files

6

Software Development Flow

10

Configuring the BSP

11

Software Naming Conventions

20

Software Architecture

21

LED write

22

Ethernet packet

22

PHY driver level interface

22

MicroC-OS/II Resources

23

■ SSSLEDCommandQ

24

■ SSSLEDFreqMailbox

24

Error Handling

26

MicroC/OS-II Internal Tasks

29

User Networking Tasks

30

User Non-Networking Tasks

30

PHY Monitoring Task

30

Task Stack Size

30

Where to Go Next

31

A. Hardware Setup Details

33

Network Connection

34

Additional Information

35

Info–2 Additional Information

36

Typographic Conventions

36

Altera Nios Ethernet Specifications (50 pages)

Brand: Altera | Category: PC/workstation barebones | Size: 0.80 MB |

English

Table of contents

Nios II Hardware Development

1

Tutorial

1

Preliminary

2

TU-N2HWDV-2.5

2

Contents

3

About this Tutorial

5

How to Contact

6

Typographic

6

Conventions

6

Visual Cue Meaning

7

Nios II Hardware

9

1–2 Altera Corporation

10

October 2007

10

OpenCore Plus Evaluation

12

Nios II System

13

Development

13

Analyzing System Requirements

14

Altera Corporation 1–7

15

1–8 Altera Corporation

16

Varying the Development Flow

17

Creating the

18

Example Design

18

Install the Design Files

19

Analyze System Requirements

20

Design Project

20

Altera Corporation 1–13

21

1–14 Altera Corporation

22

Add the On-Chip Memory

24

Altera Corporation 1–17

25

1–18 Altera Corporation

26

Altera Corporation 1–19

27

Add the JTAG UART

28

Add the Interval Timer

29

1–22 Altera Corporation

30

Add the System ID Peripheral

31

Add the PIO

32

1–26 Altera Corporation

34

Altera Corporation 1–27

35

Altera Corporation 1–29

37

Assign FPGA pins

38

Altera Corporation 1–31

39

Altera Corporation 1–33

41

1–34 Altera Corporation

42

Altera Corporation 1–35

43

Compile the Project

44

Altera Corporation 1–37

45

Run the Program

46

Altera Corporation 1–39

47

Run the Program on the ISS

48

Taking the Next

49

1–42 Altera Corporation

50

Altera devices