Altera Stratix GX Transceiver User Manual Page 245
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Altera Corporation 9β19
January 2005 Stratix GX Transceiver User Guide
Reset Control & Power Down
Figure 9β6. Transmitter Reset Sequence
The waveform in Figure 9β7 shows the functionality of the transmitter
reset sequence shown in Figure 9β6. As described in Table 9β1 on
page 9β3, the pll_areset resets the entire transceiver block, including
both the analog and digital portions of the transmitter and receiver. After
this signal is deasserted, the controller waits until the transmitter PLL is
stable (pll_locked = 1'b1) before deasserting tx_digitalreset.
This ensures that the output of the transmitter PLL is stable before
releasing any of the logic that it feeds.
Start
pll_areset = high
txdigitalreset = high
pll_areset = low
txdigitalreset = high
pll_locked = high
pll_areset = low
txdigitalreset = low
transmit_digitalreset = high
pll_areset = low
txdigitalreset = high
YES
NO
YES
NO
async_reset or sync_reset
- 101 Innovation Drive 1
- San Jose, CA 95134 1
- (408) 544-7000 1
- Contents 3
- Chapter 4. SONET Mode 4
- Chapter 5. XAUI Mode 4
- Chapter 6. GigE Mode 5
- Chapter 7. Loopback Modes 5
- About This User Guide 7
- Typographic 8
- Conventions 8
- 1. Introduction 9
- Transceiver 10
- Architecture 10
- Digital Overview 11
- Byte Serializer/Deserializer 12
- 8B/10B Encoder/Decoder 12
- Modes of 13
- Operation 13
- Loopback 17
- Built-In Self Test 17
- 1β10 Altera Corporation 18
- Modes of Operation 18
- 2. Stratix GX Analog 19
- Description 19
- Programmable Pre-Emphasis 22
- Transmitter PLL 23
- Clock Synthesis 24
- 2β8 Altera Corporation 26
- Transmitter Analog 26
- Receiver Analog 27
- 2β10 Altera Corporation 28
- Equalizer Mode 29
- Receiver PLL 30
- 2β14 Altera Corporation 32
- Receiver Bandwidth Type 33
- Clock Recovery Unit 34
- Altera Corporation 2β17 35
- Stratix GX Analog Description 35
- 2β18 Altera Corporation 36
- Altera Corporation 2β19 37
- Analog Features 38
- Notes (1)β(4) 39
- 2β22 Altera Corporation 40
- MegaWizard Analog Features 40
- Notes to Figure 2β14: 40
- Altera Corporation 2β23 41
- Note to Figure 2β15: 41
- 2β24 Altera Corporation 42
- Notes to Figure 2β16: 42
- Altera Corporation 2β25 43
- Notes to Figure 2β17: 43
- 2β26 Altera Corporation 44
- Notes to Figure 2β18: 44
- Altera Corporation 2β27 45
- 2β28 Altera Corporation 46
- 3. Basic Mode 47
- Basic Mode 48
- Manual Alignment Modes 51
- 3β6 Altera Corporation 52
- Altera Corporation 3β7 53
- 3β8 Altera Corporation 54
- 3β14 Altera Corporation 60
- Altera Corporation 3β15 61
- Byte Serializer 63
- Altera Corporation 3β21 67
- 3β22 Altera Corporation 68
- Basic Mode Clocking 68
- TX_PLL_CLK. If not available 70
- CORECLK_OUT through logic 70
- RX_CLKOUT 70
- Altera Corporation 3β25 71
- Altera Corporation 3β27 73
- 3β28 Altera Corporation 74
- 3β30 Altera Corporation 76
- Basic Mode MegaWizard Plug-In 76
- Notes to Figure 3β25: 76
- Altera Corporation 3β31 77
- Notes to Figure 3β26: 77
- 3β32 Altera Corporation 78
- Notes to Figure 3β27: 78
- Altera Corporation 3β33 79
- Notes to Figure 3β28: 79
- 3β34 Altera Corporation 80
- Notes to Figure 3β29: 80
- Altera Corporation 3β35 81
- Notes to Figure 3β30: 81
- 3β36 Altera Corporation 82
- 4. SONET Mode 83
- Altera Corporation 4β5 87
- 4β6 Altera Corporation 88
- Altera Corporation 4β7 89
- Altera Corporation 4β9 91
- 4β10 Altera Corporation 92
- Altera Corporation 4β13 95
- 4β14 Altera Corporation 96
- Altera Corporation 4β15 97
- TX_PLL_CLK. Available 98
- 4β18 Altera Corporation 100
- SONET Mode Clocking 100
- Altera Corporation 4β19 101
- SONET Mode 101
- Altera Corporation 4β21 103
- 4β22 Altera Corporation 104
- MegaWizard 105
- Plug-In Manager 105
- 4β24 Altera Corporation 106
- Notes to Figure 4β17: 106
- Altera Corporation 4β25 107
- Notes to Figure 4β18: 107
- 4β26 Altera Corporation 108
- Notes to Figure 4β19: 108
- Altera Corporation 4β27 109
- Notes to Figure 4β20: 109
- 4β28 Altera Corporation 110
- Notes to Figure 4β21: 110
- Altera Corporation 4β29 111
- Notes to Figure 4β22: 111
- 4β30 Altera Corporation 112
- 5. XAUI Mode 113
- 5β2 Altera Corporation 114
- Introduction 114
- XAUI Mode 117
- Receiver 117
- Word Aligner 118
- XAUI Synchronization Mode 119
- 5β8 Altera Corporation 120
- Note to Figure 5β6: 120
- Channel Aligner 121
- 5β10 Altera Corporation 122
- Rate Matcher 123
- 8B/10B Decoder 123
- 10-Bit Decoding 124
- Code Error Detect 124
- Disparity Error Detector 125
- Control Detect 126
- PCS - XGMII Code Conversion 127
- Byte Deserializer 127
- 5β16 Altera Corporation 128
- Altera Corporation 5β17 129
- Transmitter 130
- Altera Corporation 5β19 131
- 5β20 Altera Corporation 132
- 8B/10B Encoder 133
- 8B/10B Reset Condition 134
- Control Code Encoding 135
- Clocking 136
- Altera Corporation 5β25 137
- 5β26 Altera Corporation 138
- XAUI Mode Clocking 138
- 5β28 Altera Corporation 140
- Altera Corporation 5β29 141
- 5β30 Altera Corporation 142
- 5β32 Altera Corporation 144
- Altera Corporation 5β33 145
- Altera Corporation 5β35 147
- Notes to Figure 5β28: 147
- 5β36 Altera Corporation 148
- Notes to Figure 5β29: 148
- Altera Corporation 5β37 149
- Notes to Figure 5β30: 149
- 5β38 Altera Corporation 150
- Notes to Figure 5β31: 150
- Altera Corporation 5β39 151
- Notes to Figure 5β32: 151
- 5β40 Altera Corporation 152
- Notes to Figure 5β33: 152
- Altera Corporation 5β41 153
- 5β42 Altera Corporation 154
- 6. GigE Mode 155
- /C1/ and /C2/ code groups 156
- /K28.5/D21.5/Config_Reg (1) 156
- GigE Mode 158
- Pattern Detector Module 159
- 6β6 Altera Corporation 160
- Altera Corporation 6β7 161
- 6β8 Altera Corporation 162
- 6β10 Altera Corporation 164
- /K28.5/, /D5.6/) and 170
- 6β18 Altera Corporation 172
- Altera Corporation 6β21 175
- 6β22 Altera Corporation 176
- GigE Mode Clocking 176
- Altera Corporation 6β23 177
- Clock Port Description 178
- 6β26 Altera Corporation 180
- 6β28 Altera Corporation 182
- Altera Corporation 6β29 183
- 6β30 Altera Corporation 184
- 6β32 Altera Corporation 186
- GigE Mode MegaWizard 186
- Notes to Figure 6β27: 186
- Altera Corporation 6β33 187
- Notes to Figure 6β28: 187
- 6β34 Altera Corporation 188
- Notes to Figure 6β29: 188
- Altera Corporation 6β35 189
- Notes to Figure 6β30: 189
- 6β36 Altera Corporation 190
- Notes to Figure 6β31: 190
- Altera Corporation 6β37 191
- Notes to Figure 6β32: 191
- Design Example 192
- Altera Corporation 6β39 193
- 6β40 Altera Corporation 194
- Altera Corporation 6β41 195
- 6β42 Altera Corporation 196
- Altera Corporation 6β43 197
- 6β44 Altera Corporation 198
- Altera Corporation 6β45 199
- 6β46 Altera Corporation 200
- 7. Loopback Modes 201
- Parallel 202
- Non-Active Path 203
- Active Path 203
- Altera Corporation 8β1 205
- January 2005 205
- Notes to Figure 8β1: 205
- PRBS Mode Generator 206
- Incremental Mode Generator 207
- High-Frequency Mode Generator 207
- Low-Frequency Mode Generator 208
- Pattern Verifier 209
- Incremental Mode Verifier 210
- Examples 211
- 8β8 Altera Corporation 212
- Design Examples 212
- Altera Corporation 8β9 213
- 8β10 Altera Corporation 214
- Altera Corporation 8β11 215
- 8β12 Altera Corporation 216
- Altera Corporation 8β13 217
- 8β14 Altera Corporation 218
- Altera Corporation 8β15 219
- 8β16 Altera Corporation 220
- Altera Corporation 8β17 221
- 8β18 Altera Corporation 222
- Altera Corporation 8β19 223
- 8β20 Altera Corporation 224
- Altera Corporation 8β21 225
- 8β22 Altera Corporation 226
- 9. Reset Control & 227
- Power Down 227
- 9β2 Altera Corporation 228
- 9β4 Altera Corporation 230
- Recommended Resets 230
- Altera Corporation 9β5 231
- 9β6 Altera Corporation 232
- 9β8 Altera Corporation 234
- Altera Corporation 9β9 235
- 9β10 Altera Corporation 236
- Altera Corporation 9β11 237
- Altera Corporation 9β13 239
- 9β14 Altera Corporation 240
- Altera Corporation 9β15 241
- 9β16 Altera Corporation 242
- Altera Corporation 9β17 243
- 9β18 Altera Corporation 244
- Altera Corporation 9β19 245
- 9β20 Altera Corporation 246
- Altera Corporation 9β21 247
- Altera Corporation 248
- Altera Corporation 9β23 249
- 9β24 Altera Corporation 250
- Altera Corporation 9β25 251
- 9β26 Altera Corporation 252
- 9β28 Altera Corporation 254
- Altera Corporation 9β29 255
- 9β30 Altera Corporation 256
- Altera Corporation 9β31 257
- Receiver Reset 258
- Altera Corporation 9β33 259
- Altera Corporation 9β35 261
- 9β36 Altera Corporation 262
- Altera Corporation 9β37 263
- 9β38 Altera Corporation 264
- 9β40 Altera Corporation 266
- Altera Corporation 9β41 267
- 9β42 Altera Corporation 268
- Altera Corporation 9β43 269
- 9β44 Altera Corporation 270
- 9β46 Altera Corporation 272
- Altera Corporation 9β47 273
- 9β48 Altera Corporation 274
- 9β50 Altera Corporation 276
- Altera Corporation 9β51 277
- Transmitter Reset 278
- Altera Corporation 9β53 279
- Stable TXPLL Clock 280
- Altera Corporation 9β55 281
- 9β56 Altera Corporation 282
- 8B/10B Code 285
- Aβ2 Altera Corporation 286
- Supported Codes 287
- Aβ12 Altera Corporation 296
- Appendix B. Ports & 297
- Parameters 297
- Output Ports 301
- Parameter 305
- Descriptions 305
- port must be used 309
- Appendix C. REFCLKB Pin 311
- Constraints 311
- Cβ2 Altera Corporation 312
- Known Issues 312
- Quartus II Software Messages 313
- Recommendations 315
- Cβ6 Altera Corporation 316
- Altera Corporation Cβ7 317
- Cβ8 Altera Corporation 318
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