Altera SerialLite III Streaming MegaCore Function User Manual Page 68
- Page / 68
- Table of contents
- BOOKMARKS
- Function User Guide 1
- Contents 2
- Quick Reference 4
- Item Description 5
- Continuous Mode 7
- Burst Mode 7
- Getting Started 10
- Related Information 11
- Arria 10 Designs 12
- Parameter 13
- Value Default Description 13
- File Name Description 15
- Simulating 18
- Simulation Parameters 19
- Arria 10 Simulation Testbench 21
- UG-01126 22
- 2015.05.04 22
- Altera Corporation 23
- Send Feedback 23
- Simulator File Directory 24
- Device Family 24
- Description 25
- Core Function 26
- Source Clock Generator 28
- Source Application Module 29
- Source Adaptation Module 29
- Source PPM-Absorption Module 30
- Sink Clock Generator 31
- Sink Application Module 31
- Sink Adaptation Module 32
- Lane Alignment Module 32
- Clock Domains 34
- Core Clocking 35
- Standard Clocking Mode 36
- Advanced Clocking Mode 37
- Core Latency 38
- Device Clocking Mode 39
- Parameters 39
- Latency (ns) 39
- Link-Up Sequence 40
- CRC-32 Error Injection 41
- FIFO ECC Protection 41
- User Data Interface Waveforms 41
- Signal Width 43
- Direction Description 43
- Clock Domain 47
- Guidelines 56
- Design Example Components 58
- Design Setup 59
- Design Example Operation 61
- Source Core Link Debugging 62
- Sink Core Link Debugging 64
- Error Handling 65
- Additional Information 67
- Contact Method Address 68
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