Altera Quartus II Settings File User Manual Page 97
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HDL_INITIAL_FANOUT_LIMIT
Directs Integrated Synthesis to check the initial fan-out of each net in the netlist immediately after
elaboration but prior to any netlist optimizations. If the fan-out for a net exceeds the specified limit, then
Integrated Synthesis will issue a warning.
Type
Integer
Device Support
This setting can be used in projects targeting any Altera device family.
Notes
This assignment supports synthesis wildcards.
Syntax
set_global_assignment -name HDL_INITIAL_FANOUT_LIMIT -entity <entity name>
<value>
set_instance_assignment -name HDL_INITIAL_FANOUT_LIMIT -to <to> -entity
<entity name> <value>
Example
set_instance_assignment -name hdl_initial_fanout_limit 100 -to foo
MNL-Q21005
2015.05.04
HDL_INITIAL_FANOUT_LIMIT
97
Quartus Settings File Reference Manual
Altera Corporation
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- BOARD_MODEL_EBD_FAR_END 1
- BOARD_MODEL_EBD_FILE_NAME 2
- BOARD_MODEL_EBD_SIGNAL_NAME 3
- BOARD_MODEL_FAR_C 4
- BOARD_MODEL_FAR_PULLDOWN_R 6
- BOARD_MODEL_FAR_PULLUP_R 7
- BOARD_MODEL_FAR_SERIES_R 8
- BOARD_MODEL_NEAR_C 9
- MNL-Q21005 10
- 2015.05.04 10
- BOARD_MODEL_NEAR_PULLDOWN_R 11
- BOARD_MODEL_NEAR_PULLUP_R 12
- BOARD_MODEL_NEAR_SERIES_R 13
- BOARD_MODEL_NEAR_TLINE_LENGTH 15
- BOARD_MODEL_TERMINATION_V 17
- BOARD_MODEL_TLINE_LENGTH 19
- ENABLE_ADVANCED_IO_TIMING 21
- OUTPUT_IO_TIMING_ENDPOINT 22
- PCB_LAYER 25
- PCB_LAYERS 26
- PCB_LAYER_THICKNESS 27
- SYNCHRONOUS_GROUP 28
- ADV_NETLIST_OPT_ALLOWED 29
- ALLOW_CHILD_PARTITIONS 34
- ALLOW_POWER_UP_DONT_CARE 35
- ALLOW_SYNCH_CTRL_USAGE 37
- ALLOW_XOR_GATE_USAGE 38
- APEX20K_TECHNOLOGY_MAPPER 40
- AUTO_CARRY_CHAINS 41
- AUTO_CASCADE_CHAINS 42
- AUTO_CLOCK_ENABLE_RECOGNITION 43
- AUTO_DSP_RECOGNITION 44
- AUTO_ENABLE_SMART_COMPILE 45
- AUTO_GLOBAL_CLOCK_MAX 46
- AUTO_GLOBAL_OE_MAX 47
- AUTO_IMPLEMENT_IN_ROM 48
- AUTO_LCELL_INSERTION 49
- AUTO_OPEN_DRAIN_PINS 50
- AUTO_PARALLEL_EXPANDERS 51
- AUTO_PARALLEL_SYNTHESIS 52
- AUTO_RAM_BLOCK_BALANCING 53
- AUTO_RAM_RECOGNITION 54
- AUTO_RAM_TO_LCELL_CONVERSION 55
- AUTO_RESOURCE_SHARING 56
- AUTO_ROM_RECOGNITION 57
- BLOCK_DESIGN_NAMING 59
- CARRY_CHAIN_LENGTH 60
- CASCADE_CHAIN_LENGTH 61
- CLKLOCKX1_INPUT_FREQ 62
- DEVICE_FILTER_PACKAGE 65
- DEVICE_FILTER_PIN_COUNT 66
- DEVICE_FILTER_SPEED_GRADE 67
- DEVICE_FILTER_VOLTAGE 68
- DISABLE_OCP_HW_EVAL 70
- DONT_MERGE_REGISTER 72
- DQS_DELAY 73
- DQS_FREQUENCY 74
- DQS_SHIFT 75
- DQS_SYSTEM_CLOCK 76
- DSE_SYNTH_EXTRA_EFFORT_MODE 77
- DSP_BLOCK_BALANCING 78
- EDA_INPUT_DATA_FORMAT 80
- EDA_INPUT_GND_NAME 81
- EDA_INPUT_VCC_NAME 82
- EDA_LMF_FILE 83
- EDA_RUN_TOOL_AUTOMATICALLY 84
- EDA_SHOW_LMF_MAPPING_MESSAGES 85
- EDA_VHDL_LIBRARY 86
- ENABLE_IP_DEBUG 87
- ENABLE_M512 88
- EXTRACT_VHDL_STATE_MACHINES 90
- FLEX10K_CARRY_CHAIN_LENGTH 92
- FLEX6K_CARRY_CHAIN_LENGTH 94
- FLEX6K_OPTIMIZATION_TECHNIQUE 95
- FORCE_SYNCH_CLEAR 96
- HDL_INITIAL_FANOUT_LIMIT 97
- HDL_MESSAGE_LEVEL 98
- HDL_MESSAGE_OFF 99
- HDL_MESSAGE_ON 100
- HPS_PARTITION 101
- IGNORE_CARRY_BUFFERS 102
- IGNORE_CASCADE_BUFFERS 103
- IGNORE_GLOBAL_BUFFERS 104
- IGNORE_LCELL_BUFFERS 105
- IGNORE_MAX_FANOUT_ASSIGNMENTS 106
- IGNORE_ROW_GLOBAL_BUFFERS 107
- IGNORE_SOFT_BUFFERS 108
- IMPLEMENT_AS_CLOCK_ENABLE 111
- INFER_RAMS_FROM_RAW_LOGIC 113
- IP_SEARCH_PATHS 114
- LCELL_INSERTION 115
- MAX7000_FANIN_PER_CELL 117
- MAX7000_IGNORE_LCELL_BUFFERS 118
- MAX7000_IGNORE_SOFT_BUFFERS 119
- MAXII_OPTIMIZATION_TECHNIQUE 122
- MAX_BALANCING_DSP_BLOCKS 124
- MAX_FANOUT 125
- MAX_LABS 126
- MAX_RAM_BLOCKS_M4K 128
- MAX_RAM_BLOCKS_M512 129
- MAX_RAM_BLOCKS_MRAM 130
- MERCURY_CARRY_CHAIN_LENGTH 131
- ETTING_DONT_CARE 133
- MUX_RESTRUCTURE 134
- NOT_GATE_PUSH_BACK 135
- OPTIMIZATION_TECHNIQUE 140
- PARALLEL_SYNTHESIS 143
- PARAMETER 144
- POWER_UP_LEVEL 145
- PRESERVE_FANOUT_FREE_NODE 146
- PRESERVE_REGISTER 147
- PRE_MAPPING_RESYNTHESIS 148
- PRPOF_ID 149
- REMOVE_DUPLICATE_REGISTERS 151
- REMOVE_REDUNDANT_LOGIC_CELLS 152
- REPORT_CONNECTIVITY_CHECKS 153
- REPORT_PARAMETER_SETTINGS 154
- REPORT_SOURCE_ASSIGNMENTS 155
- RESYNTHESIS_RETIMING 158
- SAFE_STATE_MACHINE 159
- SAVE_DISK_SPACE 160
- SEARCH_PATH 161
- STATE_MACHINE_PROCESSING 164
- LD_SELECT 165
- STRATIXII_CARRY_CHAIN_LENGTH 166
- STRATIX_CARRY_CHAIN_LENGTH 168
- STRICT_RAM_RECOGNITION 170
- SYNTHESIS_EFFORT 172
- SYNTH_CLOCK_MUX_PROTECTION 175
- SYNTH_GATED_CLOCK_CONVERSION 176
- SYNTH_MESSAGE_LEVEL 177
- SYNTH_PROTECT_SDC_CONSTRAINT 178
- SYNTH_TIMING_DRIVEN_SYNTHESIS 180
- TOP_LEVEL_ENTITY 181
- TRUE_WYSIWYG_FLOW 182
- USER_LIBRARIES 183
- USE_HIGH_SPEED_ADDER 185
- VERILOG_CONSTANT_LOOP_LIMIT 187
- VERILOG_INPUT_VERSION 188
- VERILOG_LMF_FILE 189
- VERILOG_MACRO 190
- VHDL_INPUT_LIBRARY 193
- VHDL_INPUT_VERSION 194
- VHDL_LMF_FILE 195
- Assembler Assignments 197
- APEX20K_JTAG_USER_CODE 199
- AUTO_RESTART_CONFIGURATION 202
- CLOCK_SOURCE 203
- COMPRESSION_MODE 204
- CONFIGURATION_CLOCK_DIVISOR 205
- CONFIGURATION_CLOCK_FREQUENCY 206
- CYCLONEII_M4K_COMPATIBILITY 208
- CYCLONE_CONFIGURATION_DEVICE 209
- ENABLE_ADV_SEU_DETECTION 211
- ENABLE_AUTONOMOUS_PCIE_HIP 212
- ENABLE_OCT_DONE 215
- EN_SPI_IO_WEEK_PULLUP 216
- EN_USER_IO_WEEK_PULLUP 217
- FLEX10K_CONFIGURATION_DEVICE 219
- FLEX10K_JTAG_USER_CODE 222
- FLEX6K_CONFIGURATION_DEVICE 223
- GENERATE_HEX_FILE 225
- GENERATE_RBF_FILE 226
- GENERATE_TTF_FILE 227
- HEXOUT_FILE_COUNT_DIRECTION 229
- HEXOUT_FILE_START_ADDRESS 230
- MAX7000S_JTAG_USER_CODE 231
- MAX7000_JTAG_USER_CODE 232
- MERCURY_CONFIGURATION_DEVICE 234
- MERCURY_JTAG_USER_CODE 236
- POF_VERIFY_PROTECT 238
- POR_SCHEME 239
- SECURITY_BIT 242
- STRATIXII_MRAM_COMPATIBILITY 244
- STRATIX_CONFIGURATION_DEVICE 245
- STRATIX_JTAG_USER_CODE 247
- USE_CHECKSUM_AS_USERCODE 249
- USE_CONFIGURATION_DEVICE 250
- Assignment Group Assignments 251
- ASSIGNMENT_GROUP_MEMBER 252
- Classic Timing Assignments 253
- CUT_OFF_IO_PIN_FEEDBACK 254
- DEFAULT_HOLD_MULTICYCLE 257
- DO_COMBINED_ANALYSIS 258
- INPUT_TRANSITION_TIME 260
- LVDS_FIXED_CLOCK_DATA_PHASE 261
- MAX_CORE_JUNCTION_TEMP 262
- MIN_CORE_JUNCTION_TEMP 263
- NOMINAL_CORE_SUPPLY_VOLTAGE 264
- PACKAGE_SKEW_COMPENSATION 265
- TIMEQUEST_DO_CCPP_REMOVAL 268
- TIMEQUEST_DO_REPORT_TIMING 269
- TIMEQUEST_REPORT_SCRIPT 272
- Compiler Assignments 276
- ALLOW_REGISTER_MERGING 277
- OPTIMIZATION_MODE 278
- TIMEQUEST2 279
- Design Assistant Assignments 280
- ACLK_RULE_IMSZER_ADOMAIN 281
- ACLK_RULE_NO_SZER_ACLK_DOMAIN 282
- CLK_RULE_CLKNET_CLKSPINES 285
- CLK_RULE_COMB_CLOCK 287
- CLK_RULE_GATED_CLK_FANOUT 288
- CLK_RULE_INPINS_CLKNET 289
- CLK_RULE_INV_CLOCK 290
- CLK_RULE_MIX_EDGES 291
- DA_CUSTOM_RULE_FILE 292
- DISABLE_DA_GX_RULE 293
- DISABLE_DA_RULE 294
- DRC_DEADLOCK_STATE_LIMIT 295
- DRC_DETAIL_MESSAGE_LIMIT 296
- DRC_FANOUT_EXCEEDING 297
- DRC_GATED_CLOCK_FEED 298
- DRC_REPORT_FANOUT_EXCEEDING 299
- DRC_REPORT_TOP_FANOUT 300
- DRC_TOP_FANOUT 301
- DRC_VIOLATION_MESSAGE_LIMIT 302
- ENABLE_DA_RULE 303
- ENABLE_DRC_SETTINGS 304
- FSM_RULE_DEADLOCK_STATE 306
- FSM_RULE_NO_RESET_STATE 307
- FSM_RULE_NO_SZER_ACLK_DOMAIN 308
- FSM_RULE_UNREACHABLE_STATE 309
- FSM_RULE_UNUSED_TRANSITION 310
- HARDCOPY_FLOW_AUTOMATION 311
- HARDCOPY_NEW_PROJECT_PATH 312
- HCPY_CAT 313
- HCPY_VREF_PINS 315
- NONSYNCHSTRUCT_CAT 316
- NONSYNCHSTRUCT_RULE_ASYN_RAM 317
- NONSYNCHSTRUCT_RULE_COMBLOOP 318
- NONSYNCHSTRUCT_RULE_REG_LOOP 324
- NONSYNCHSTRUCT_RULE_SRLATCH 326
- RESET_CAT 327
- RESET_RULE_COMB_ASYNCH_RESET 328
- RESET_RULE_IMSYNCH_EXRESET 330
- RESET_RULE_UNSYNCH_EXRESET 332
- SIGNALRACE_CAT 333
- SIGNALRACE_RULE_CLK_PORT_RACE 334
- SIGNALRACE_RULE_RESET_RACE 335
- SIGNALRACE_RULE_TRISTATE 337
- TIMING_CAT 338
- EDA_BOARD_DESIGN_SYMBOL_TOOL 342
- EDA_BOARD_DESIGN_TIMING_TOOL 343
- EDA_BOARD_DESIGN_TOOL 344
- EDA_DESIGN_INSTANCE_NAME 346
- EDA_ENABLE_GLITCH_FILTERING 347
- EDA_ENABLE_IPUTF_MODE 348
- EDA_EXTRA_ELAB_OPTION 349
- EDA_FLATTEN_BUSES 350
- EDA_FORMAL_VERIFICATION_TOOL 352
- EDA_FV_HIERARCHY 353
- EDA_GENERATE_POWER_INPUT_FILE 356
- EDA_IBIS_MODEL_SELECTOR 359
- EDA_IBIS_MUTUAL_COUPLING 360
- EDA_IPFS_FILE 362
- EDA_LAUNCH_CMD_LINE_TOOL 363
- EDA_MAINTAIN_DESIGN_HIERARCHY 364
- EDA_MAP_ILLEGAL_CHARACTERS 365
- EDA_NETLIST_WRITER_OUTPUT_DIR 370
- EDA_RESYNTHESIS_TOOL 371
- EDA_RTL_SIMULATION_RUN_SCRIPT 372
- EDA_RTL_SIM_MODE 373
- EDA_RTL_TEST_BENCH_FILE_NAME 374
- EDA_RTL_TEST_BENCH_NAME 375
- EDA_RTL_TEST_BENCH_RUN_FOR 376
- EDA_SDC_FILE_NAME 377
- EDA_SIMULATION_RUN_SCRIPT 379
- EDA_SIMULATION_TOOL 380
- EDA_TEST_BENCH_ENABLE_STATUS 385
- EDA_TEST_BENCH_FILE 388
- EDA_TEST_BENCH_FILE_NAME 389
- EDA_TEST_BENCH_MODULE_NAME 391
- EDA_TEST_BENCH_NAME 392
- EDA_TEST_BENCH_RUN_FOR 393
- EDA_TEST_BENCH_RUN_SIM_FOR 394
- EDA_TIME_SCALE 395
- EDA_TIMING_ANALYSIS_TOOL 396
- EDA_VHDL_ARCH_NAME 399
- EQC_AUTO_BREAK_CONE 404
- EQC_AUTO_COMP_LOOP_CUT 405
- EQC_AUTO_INVERSION 406
- EQC_AUTO_PORTSWAP 407
- EQC_AUTO_TERMINATE 408
- EQC_BBOX_MERGE 409
- EQC_CONSTANT_DFF_DETECTION 410
- EQC_DETECT_DONT_CARES 411
- EQC_DFF_SS_EMULATION 412
- EQC_DUPLICATE_DFF_DETECTION 413
- EQC_LVDS_MERGE 414
- EQC_MAC_REGISTER_UNPACK 415
- EQC_PARAMETER_CHECK 416
- EQC_POWER_UP_COMPARE 417
- EQC_RAM_REGISTER_UNPACK 418
- EQC_RAM_UNMERGING 419
- EQC_RENAMING_RULES 420
- EQC_RENAMING_RULES_LIST 421
- EQC_SHOW_ALL_MAPPED_POINTS 423
- EQC_STRUCTURE_MATCHING 424
- EQC_SUB_CONE_REPORT 425
- Fitter Assignments 426
- ADCE_ENABLED 427
- ALM_REGISTER_PACKING_EFFORT 430
- ALWAYS_ENABLE_INPUT_BUFFERS 431
- APEX20KE_DEVICE_IO_STANDARD 432
- APEX20K_CONFIGURATION_SCHEME 433
- APEX20K_DEVICE_IO_STANDARD 435
- APEXII_CONFIGURATION_SCHEME 436
- APEXII_DEVICE_IO_STANDARD 437
- ASYNC_PIPELINE_REG_REACH 439
- AUTO_C3_M9K_BIT_SKIP 440
- AUTO_DELAY_CHAINS 441
- AUTO_GLOBAL_CLOCK 443
- AUTO_GLOBAL_MEMORY_CONTROLS 444
- AUTO_GLOBAL_OE 445
- AUTO_GLOBAL_REGISTER_CONTROLS 446
- AUTO_MERGE_PLLS 447
- AUTO_PACKED_REGISTERS_MAX 448
- Default Value 449
- AUTO_TURBO_BIT 450
- C3_M9K_BIT_SKIP 455
- CARRY_OUT_PINS_LCELL_INSERT 456
- CDR_BANDWIDTH_PRESET 457
- CKN_CK_PAIR 458
- CLAMPING_DIODE 459
- CLOCK_ENABLE_ROUTING 460
- CLOCK_REGION 461
- CLOCK_TO_OUTPUT_DELAY 462
- CONFIGURATION_VCCIO_LEVEL 463
- CRC_ERROR_CHECKING 464
- CRC_ERROR_OPEN_DRAIN 465
- CURRENT_STRENGTH_NEW 466
- CVP_CONFDONE_OPEN_DRAIN 467
- CVP_MODE 468
- CYCLONEII_TERMINATION 472
- CYCLONE_CONFIGURATION_SCHEME 473
- D1_DELAY 474
- D1_FINE_DELAY 475
- D2_DELAY 476
- D3_DELAY 477
- D4_DELAY 478
- D4_FINE_DELAY 479
- D5_DELAY 480
- D5_FINE_DELAY 481
- D5_OCT_DELAY 482
- D5_OE_DELAY 483
- D6_DELAY 484
- D6_FINE_DELAY 485
- D6_OCT_DELAY 486
- D6_OE_DELAY 487
- D6_OE_FINE_DELAY 488
- DATA0_PIN 489
- DCLK_PIN 490
- DDIO_INPUT_REGISTER 492
- DDIO_OUTPUT_REGISTER 493
- DDIO_OUTPUT_REGISTER_DISTANCE 494
- DEVICE_INITIALIZATION_CLOCK 499
- DEVICE_MIGRATION_LIST 500
- DPRIO_CHANNEL_NUM 503
- DPRIO_CRUCLK_NUM 504
- DPRIO_INTERFACE_REG 505
- DPRIO_QUAD_NUM 506
- DPRIO_QUAD_PLL_NUM 507
- DPRIO_TX_PLL0_REFCLK_NUM 508
- DPRIO_TX_PLL1_REFCLK_NUM 509
- DPRIO_TX_PLL_NUM 510
- DQSB_DQS_PAIR 511
- DQSOUT_DELAY_CHAIN 512
- DQS_ENABLE_DELAY_CHAIN 513
- DQS_LOCAL_CLOCK_DELAY_CHAIN 514
- DQ_GROUP 515
- DUAL_PURPOSE_CLOCK_PIN_DELAY 517
- DUPLICATE_ATOM 518
- DYNAMIC_OCT_CONTROL_GROUP 519
- ECO_ALLOW_ROUTING_CHANGES 520
- ECO_OPTIMIZE_TIMING 521
- ECO_REGENERATE_REPORT 522
- ENABLE_ASMI_FOR_FLASH_LOADER 523
- ENABLE_BOOT_SEL_PIN 525
- ENABLE_BUS_HOLD_CIRCUITRY 526
- ENABLE_CONFIGURATION_PINS 527
- ENABLE_CRC_ERROR_PIN 528
- ENABLE_CVP_CONFDONE 529
- ENABLE_DEVICE_WIDE_OE 530
- ENABLE_DEVICE_WIDE_RESET 531
- ENABLE_HOLD_BACK_OFF 532
- ENABLE_INIT_DONE_OUTPUT 533
- ENABLE_JTAG_BST_SUPPORT 534
- ENABLE_JTAG_PIN_SHARING 535
- ENABLE_NCEO_OUTPUT 536
- ENABLE_NCE_PIN 537
- ENABLE_NCONFIG_FROM_CORE 538
- ENABLE_PR_PINS 539
- ENABLE_VREFA_PIN 540
- ENABLE_VREFB_PIN 541
- ERROR_CHECK_FREQUENCY_DIVISOR 542
- EXCLUSIVE_IO_GROUP 543
- EXTERNAL_LVDS_RX_USES_DPA 545
- FALLBACK_TO_EXTERNAL_FLASH 546
- FASTROW_INTERCONNECT 547
- FINAL_PLACEMENT_OPTIMIZATION 548
- FITTER_EFFORT 553
- FIT_ATTEMPTS_TO_SKIP 554
- FIT_ONLY_ONE_ATTEMPT 555
- FLEX10K_CONFIGURATION_SCHEME 556
- FLEX10K_DEVICE_IO_STANDARD 558
- FLEX10K_ENABLE_LOCK_OUTPUT 559
- FLEX10K_MAX_PERIPHERAL_OE 560
- FLEX6K_CONFIGURATION_SCHEME 561
- FLEX6K_DEVICE_IO_STANDARD 563
- FORCE_CONFIGURATION_VCCIO 564
- FORCE_MERGE_PLL 567
- FORCE_MERGE_PLL_FANOUTS 568
- FORM_DDR_CLUSTERING_CLIQUE 570
- GENERATE_GXB_RECONFIG_MIF 571
- GLOBAL_SIGNAL 573
- GNDIO_CURRENT_1PT8V 575
- GNDIO_CURRENT_2PT5V 576
- GNDIO_CURRENT_GTL 577
- GNDIO_CURRENT_GTL_PLUS 578
- GNDIO_CURRENT_LVCMOS 579
- GNDIO_CURRENT_LVTTL 580
- GNDIO_CURRENT_PCI 581
- GNDIO_CURRENT_SSTL2_CLASS1 582
- GNDIO_CURRENT_SSTL2_CLASS2 583
- GNDIO_CURRENT_SSTL3_CLASS1 584
- GNDIO_CURRENT_SSTL3_CLASS2 585
- GXB_0PPM_CLOCK_GROUP 587
- GXB_0PPM_CLOCK_GROUP_DRIVER 588
- GXB_0PPM_CORECLK 589
- GXB_0PPM_CORE_CLOCK 590
- GXB_CLOCK_GROUP 591
- GXB_CLOCK_GROUP_DRIVER 592
- GXB_RECONFIG_GROUP 593
- GXB_RECONFIG_MIF 594
- GXB_RECONFIG_MIF_PLL 595
- GXB_RESERVED_TRANSMIT_CHANNEL 597
- GXB_TX_PLL_RECONFIG_GROUP 598
- IGNORE_MODE_FOR_MERGE 600
- INCREASE_DELAY_TO_OUTPUT_PIN 603
- INC_PLC_MODE 609
- INIT_DONE_OPEN_DRAIN 610
- INPUT_DELAY_CHAIN 611
- INPUT_REFERENCE 612
- INPUT_TERMINATION 613
- INSERT_ADDITIONAL_LOGIC_CELL 614
- INTERNAL_FLASH_UPDATE_MODE 615
- INTERNAL_SCRUBBING 616
- IO_MAXIMUM_TOGGLE_RATE 619
- IO_PLACEMENT_OPTIMIZATION 620
- IO_STANDARD 621
- LVDS_DIRECT_LOOPBACK_MODE 622
- LVDS_RX_REGISTER 623
- MATCH_PLL_COMPENSATION_CLOCK 625
- MAX7000B_VCCIO_IOBANK1 627
- MAX7000B_VCCIO_IOBANK2 628
- MAX7000_DEVICE_IO_STANDARD 629
- MAX7000_INDIVIDUAL_TURBO_BIT 631
- MAX_CLOCKS_ALLOWED 632
- MAX_GLOBAL_CLOCKS_ALLOWED 637
- MAX_PERIPHERY_CLOCKS_ALLOWED 638
- MAX_REGIONAL_CLOCKS_ALLOWED 639
- MERCURY_CONFIGURATION_SCHEME 642
- MERCURY_DEVICE_IO_STANDARD 644
- MIGRATION_DEVICES 647
- NCEO_OPEN_DRAIN 648
- NDQS_LOCAL_CLOCK_DELAY_CHAIN 649
- NORMAL_LCELL_INSERT 650
- OE_DELAY_CHAIN 651
- OPTIMIZE_FOR_METASTABILITY 652
- OPTIMIZE_HOLD_TIMING 653
- OPTIMIZE_MULTI_CORNER_TIMING 655
- OPTIMIZE_POWER_DURING_FITTING 656
- OPTIMIZE_SSN 657
- OPTIMIZE_TIMING 658
- OUTPUT_BUFFER_DELAY 659
- OUTPUT_BUFFER_DELAY_CONTROL 660
- OUTPUT_DELAY_CHAIN 661
- OUTPUT_ENABLE_DELAY 662
- OUTPUT_ENABLE_GROUP 663
- OUTPUT_ENABLE_ROUTING 665
- OUTPUT_PIN_LOAD 666
- OUTPUT_TERMINATION 667
- PAD_TO_CORE_DELAY 669
- PAD_TO_DDIO_REGISTER_DELAY 670
- PAD_TO_INPUT_REGISTER_DELAY 671
- PHYSICAL_SYNTHESIS_EFFORT 676
- PHYSICAL_SYNTHESIS_LOG_FILE 677
- PLACEMENT_EFFORT_MULTIPLIER 681
- PLL_AUTO_RESET 682
- PLL_BANDWIDTH_PRESET 683
- PLL_CHANNEL_SPACING 684
- PLL_COMPENSATE 685
- PLL_COMPENSATION_MODE 686
- PLL_ENFORCE_USER_PHASE_SHIFT 687
- PLL_FEEDBACK_CLOCK_SIGNAL 688
- PLL_FORCE_OUTPUT_COUNTER 689
- PLL_IGNORE_MIGRATION_DEVICES 691
- PLL_OUTPUT_CLOCK_FREQUENCY 693
- PLL_PFD_CLOCK_FREQUENCY 694
- PLL_TYPE 695
- PLL_VCO_CLOCK_FREQUENCY 696
- PRESERVE_PLL_COUNTER_ORDER 697
- PROGRAMMABLE_PREEMPHASIS 700
- PROGRAMMABLE_VOD 701
- PR_DONE_OPEN_DRAIN 702
- PR_ERROR_OPEN_DRAIN 703
- PR_PINS_OPEN_DRAIN 704
- PR_READY_OPEN_DRAIN 705
- QDR_D_PIN_GROUP 706
- QII_AUTO_PACKED_REGISTERS 707
- RESERVE_ALL_UNUSED_PINS 709
- ROUTER_EFFORT_MULTIPLIER 727
- ROUTER_REGISTER_DUPLICATION 729
- ROW_GLOBAL_SIGNAL 731
- RZQ_GROUP 732
- SLEW_RATE 736
- SLOW_SLEW_RATE 737
- _DATA_WIDTH_MODE 747
- STRATIXGX_TERMINATION_VALUE 752
- STRATIXIIGX_TERMINATION_VALUE 753
- STRATIXIII_MRAM_COMPATIBILITY 755
- STRATIXIII_UPDATE_MODE 756
- STRATIXII_TERMINATION 758
- STRATIXV_CONFIGURATION_SCHEME 759
- STRATIX_CONFIGURATION_SCHEME 760
- STRATIX_DEVICE_IO_STANDARD 762
- STRATIX_UPDATE_MODE 763
- SYNCHRONIZER_IDENTIFICATION 764
- SYNCHRONIZER_TOGGLE_RATE 766
- T11_0_DELAY 767
- T11_1_DELAY 768
- T11_DELAY 769
- T11_FINE_DELAY 770
- T4_DELAY 771
- T8_DELAY0 772
- T8_DELAY1 773
- TERMINATION 774
- TERMINATION_CONTROL_BLOCK 775
- TREAT_BIDIR_AS_OUTPUT 776
- TRI_STATE_SPI_PINS 777
- TURBO_BIT 778
- TXPMA_SLEW_RATE 779
- UNFORCE_MERGE_PLL 780
- UNUSED_TSD_PINS_GND 782
- USER_START_UP_CLOCK 783
- VCCIO_CURRENT_1PT8V 784
- VCCIO_CURRENT_2PT5V 785
- VCCIO_CURRENT_GTL 786
- VCCIO_CURRENT_GTL_PLUS 787
- VCCIO_CURRENT_LVCMOS 788
- VCCIO_CURRENT_LVTTL 789
- VCCIO_CURRENT_PCI 790
- VCCIO_CURRENT_SSTL2_CLASS1 791
- VCCIO_CURRENT_SSTL2_CLASS2 792
- VCCIO_CURRENT_SSTL3_CLASS1 793
- VCCIO_CURRENT_SSTL3_CLASS2 794
- VCCPD_VOLTAGE 795
- VREF_MODE 796
- WEAK_PULL_UP_RESISTOR 797
- XCVR_A10_REFCLK_TERM_TRISTATE 798
- Altera Corporation 799
- Send Feedback 799
- XCVR_A10_RX_ADP_DFE_FXTAP1 802
- XCVR_A10_RX_ADP_DFE_FXTAP2 806
- XCVR_A10_RX_ADP_DFE_FXTAP3 810
- XCVR_A10_RX_ADP_DFE_FXTAP4 814
- XCVR_A10_RX_ADP_DFE_FXTAP5 816
- XCVR_A10_RX_ADP_DFE_FXTAP6 818
- XCVR_A10_RX_ADP_DFE_FXTAP7 820
- XCVR_A10_RX_ADP_VGA_SEL 822
- XCVR_A10_RX_EQ_DC_GAIN_TRIM 823
- XCVR_A10_RX_LINK 825
- XCVR_A10_RX_ONE_STAGE_ENABLE 826
- XCVR_A10_RX_TERM_SEL 827
- XCVR_A10_TX_COMPENSATION_EN 828
- XCVR_A10_TX_LINK 829
- XCVR_ANALOG_SETTINGS_PROTOCOL 839
- XCVR_GT_IO_PIN_TERMINATION 842
- XCVR_GT_RX_CTLE 844
- XCVR_GT_RX_DC_GAIN 845
- XCVR_GT_TX_PRE_EMP_PRE_TAP 849
- XCVR_GT_TX_VOD_MAIN_TAP 850
- XCVR_IO_PIN_TERMINATION 851
- XCVR_RECONFIG_GROUP 852
- XCVR_REFCLK_PIN_TERMINATION 853
- XCVR_RX_ACGAIN_A 854
- XCVR_RX_ACGAIN_V 855
- XCVR_RX_BYPASS_EQ_STAGES_234 856
- XCVR_RX_COMMON_MODE_VOLTAGE 857
- XCVR_RX_DC_GAIN 858
- XCVR_RX_EQ_BW_SEL 860
- XCVR_RX_INPUT_VCM_SEL 861
- XCVR_RX_SD_ENABLE 863
- XCVR_RX_SD_OFF 864
- XCVR_RX_SD_ON 865
- XCVR_RX_SD_THRESHOLD 866
- XCVR_RX_SEL_HALF_BW 867
- XCVR_TX_COMMON_MODE_VOLTAGE 868
- XCVR_TX_PLL_RECONFIG_GROUP 869
- XCVR_TX_PRE_EMP_1ST_POST_TAP 870
- XCVR_TX_PRE_EMP_2ND_POST_TAP 871
- XCVR_TX_PRE_EMP_INV_2ND_TAP 873
- XCVR_TX_PRE_EMP_INV_PRE_TAP 874
- XCVR_TX_PRE_EMP_PRE_TAP 875
- XCVR_TX_PRE_EMP_PRE_TAP_USER 876
- XCVR_TX_RX_DET_ENABLE 877
- XCVR_TX_RX_DET_MODE 878
- XCVR_TX_RX_DET_OUTPUT_SEL 879
- XCVR_TX_SLEW_RATE_CTRL 880
- XCVR_TX_VCM_CTRL_SRC 881
- XCVR_TX_VOD 882
- XCVR_TX_VOD_PRE_EMP_CTRL_SRC 883
- XCVR_VCCA_VOLTAGE 884
- XCVR_VCCR_VCCT_VOLTAGE 885
- XSTL_INPUT_ALLOW_SE_BUFFER 886
- ALLOW_MULTIPLE_PERSONAS 888
- CROSS_BOUNDARY_OPTIMIZATIONS 890
- ENABLE_STRICT_PRESERVATION 892
- EXTENDS_TOP_BLOCK 893
- IGNORE_PARTITIONS 894
- IMPORT_BLOCK 895
- INPUT_PERSONA 902
- INSERT_BOUNDARY_WIRE_LUTS 903
- MERGE_EQUIVALENT_BIDIRS 904
- MERGE_EQUIVALENT_INPUTS 905
- PARTITION_ASD_REGION_ID 908
- PARTITION_HIERARCHY 911
- PARTITION_IMPORT_ASSIGNMENTS 913
- PARTITION_IMPORT_FILE 916
- PARTITION_LAST_IMPORTED_FILE 918
- PARTITION_NETLIST_TYPE 919
- PROPAGATE_CONSTANTS_ON_INPUTS 921
- QDB_FILE 923
- QDB_PATH 924
- QHD_MODE 925
- LogicLock Region Assignments 928
- LL_CORE_ONLY 929
- LL_ENABLED 930
- LL_HEIGHT 931
- LL_MEMBER_EXCEPTIONS 932
- LL_MEMBER_OF 933
- LL_ORIGIN 935
- LL_PARENT 936
- LL_PRIORITY 937
- LL_RESERVED 938
- LL_ROOT_REGION 939
- LL_STATE 940
- LL_WIDTH 941
- Migration Assignments 942
- MIGRATION_AUTO_PORT_SWAP 943
- MIGRATION_RAM_INFORMATION 944
- Netlist Viewer Assignments 945
- RTLV_GROUP_RELATED_NODES 947
- RTLV_GROUP_RELATED_NODES_TMV 948
- RTLV_SIMPLIFIED_LOGIC 950
- APEX20K_CLIQUE_TYPE 951
- APEX20K_LOCAL_ROUTING_SOURCE 952
- FAST_INPUT_REGISTER 953
- FAST_OCT_REGISTER 954
- FAST_OUTPUT_ENABLE_REGISTER 955
- FAST_OUTPUT_REGISTER 956
- FLEX10K_CLIQUE_TYPE 957
- FLEX6K_CLIQUE_TYPE 958
- FLEX6K_LOCAL_ROUTING_SOURCE 959
- IP_DEBUG_VISIBLE 960
- LOCATION 962
- MAX7K_CLIQUE_TYPE 963
- MEMBER_OF 964
- MERCURY_CLIQUE_TYPE 965
- PIN_CONNECT_FROM_NODE 966
- RESERVE_PIN 967
- SUBCLIQUE_OF 968
- VIRTUAL_PIN 969
- Power Estimation Assignments 970
- POWER_AUTO_COMPUTE_TJ 971
- POWER_BOARD_TEMPERATURE 972
- POWER_BOARD_THERMAL_MODEL 973
- POWER_DEFAULT_TOGGLE_RATE 975
- POWER_HPS_DYNAMIC_POWER_DUAL 977
- POWER_HPS_ENABLE 979
- POWER_HPS_PROC_FREQ 981
- POWER_HPS_STATIC_POWER 982
- POWER_HPS_TOTAL_POWER 983
- POWER_HSSI 984
- POWER_HSSI_LEFT 985
- POWER_HSSI_RIGHT 986
- POWER_HSSI_VCCHIP_LEFT 987
- POWER_HSSI_VCCHIP_RIGHT 988
- POWER_INPUT_FILE_NAME 989
- POWER_INPUT_FILE_TYPE 990
- POWER_INPUT_SAF_NAME 991
- POWER_INPUT_VCD_FILE_NAME 992
- POWER_OCS_VALUE 993
- POWER_OJB_VALUE 994
- POWER_OJC_VALUE 995
- POWER_OSA_VALUE 996
- POWER_OUTPUT_SAF_NAME 997
- POWER_PRESET_COOLING_SOLUTION 998
- POWER_READ_INPUT_FILE 999
- POWER_REPORT_SIGNAL_ACTIVITY 1001
- POWER_STATIC_PROBABILITY 1004
- POWER_TJ_VALUE 1005
- POWER_TOGGLE_RATE 1006
- POWER_TOGGLE_RATE_PERCENTAGE 1007
- POWER_USE_INPUT_FILE 1010
- POWER_USE_INPUT_FILES 1011
- POWER_USE_PVA 1012
- POWER_USE_TA_VALUE 1013
- POWER_VCCAUX_USER_OPTION 1014
- POWER_VCCA_GXBL_USER_OPTION 1015
- POWER_VCCA_GXBR_USER_OPTION 1016
- POWER_VCCA_GXB_USER_OPTION 1017
- POWER_VCCA_L_USER_OPTION 1018
- POWER_VCCA_R_USER_OPTION 1019
- POWER_VCCCB_USER_OPTION 1020
- POWER_VCCH_GXBL_USER_OPTION 1021
- POWER_VCCH_GXBR_USER_OPTION 1022
- POWER_VCCH_GXB_USER_OPTION 1023
- POWER_VCCIO_USER_OPTION 1024
- POWER_VCCL_GXB_USER_OPTION 1025
- POWER_VCCPD_USER_OPTION 1026
- POWER_VCCR_GXBL_USER_OPTION 1027
- POWER_VCCR_GXBR_USER_OPTION 1028
- POWER_VCCR_GXB_USER_OPTION 1029
- POWER_VCCT_GXBL_USER_OPTION 1030
- POWER_VCCT_GXBR_USER_OPTION 1031
- POWER_VCCT_GXB_USER_OPTION 1032
- POWER_VCD_FILE_END_TIME 1033
- POWER_VCD_FILE_START_TIME 1034
- POWER_VCD_FILTER_GLITCHES 1035
- VCCAUX_SHARED_USER_VOLTAGE 1036
- VCCAUX_USER_VOLTAGE 1037
- VCCA_FPLL_USER_VOLTAGE 1038
- VCCA_GTBR_USER_VOLTAGE 1039
- VCCA_GTB_USER_VOLTAGE 1040
- VCCA_GXBL_USER_VOLTAGE 1041
- VCCA_GXBR_USER_VOLTAGE 1042
- VCCA_GXB_USER_VOLTAGE 1043
- VCCA_L_USER_VOLTAGE 1044
- VCCA_PLL_USER_VOLTAGE 1045
- VCCA_R_USER_VOLTAGE 1046
- VCCA_USER_VOLTAGE 1047
- VCCBAT_USER_VOLTAGE 1048
- VCCCB_USER_VOLTAGE 1049
- VCCD_FPLL_USER_VOLTAGE 1050
- VCCD_PLL_USER_VOLTAGE 1051
- VCCD_USER_VOLTAGE 1052
- VCCEH_GXBL_USER_VOLTAGE 1053
- VCCEH_GXBR_USER_VOLTAGE 1054
- VCCEH_GXB_USER_VOLTAGE 1055
- VCCE_GXBL_USER_VOLTAGE 1056
- VCCE_GXBR_USER_VOLTAGE 1057
- VCCE_GXB_USER_VOLTAGE 1058
- VCCE_USER_VOLTAGE 1059
- VCCHIP_L_USER_VOLTAGE 1060
- VCCHIP_R_USER_VOLTAGE 1061
- VCCHIP_USER_VOLTAGE 1062
- VCCHSSI_L_USER_VOLTAGE 1063
- VCCHSSI_R_USER_VOLTAGE 1064
- VCCH_GTBR_USER_VOLTAGE 1065
- VCCH_GTB_USER_VOLTAGE 1066
- VCCH_GXBL_USER_VOLTAGE 1067
- VCCH_GXBR_USER_VOLTAGE 1068
- VCCH_GXB_USER_VOLTAGE 1069
- VCCH_L_USER_VOLTAGE 1070
- VCCH_R_USER_VOLTAGE 1071
- VCCINT_USER_VOLTAGE 1072
- VCCIO_USER_VOLTAGE 1073
- VCCL_GTBL_USER_VOLTAGE 1074
- VCCL_GTBR_USER_VOLTAGE 1075
- VCCL_GTB_USER_VOLTAGE 1076
- VCCL_GXBL_USER_VOLTAGE 1077
- VCCL_GXBR_USER_VOLTAGE 1078
- VCCL_GXB_USER_VOLTAGE 1079
- VCCL_USER_VOLTAGE 1080
- VCCPD_USER_VOLTAGE 1081
- VCCPGM_USER_VOLTAGE 1082
- VCCPLL_HPS_USER_VOLTAGE 1083
- VCCPT_USER_VOLTAGE 1084
- VCCP_USER_VOLTAGE 1085
- VCCRSTCLK_HPS_USER_VOLTAGE 1086
- VCCR_GTBL_USER_VOLTAGE 1087
- VCCR_GTBR_USER_VOLTAGE 1088
- VCCR_GTB_USER_VOLTAGE 1089
- VCCR_GXBL_USER_VOLTAGE 1090
- VCCR_GXBR_USER_VOLTAGE 1091
- VCCR_GXB_USER_VOLTAGE 1092
- VCCR_L_USER_VOLTAGE 1093
- VCCR_R_USER_VOLTAGE 1094
- VCCR_USER_VOLTAGE 1095
- VCCT_GTBL_USER_VOLTAGE 1096
- VCCT_GTBR_USER_VOLTAGE 1097
- VCCT_GTB_USER_VOLTAGE 1098
- VCCT_GXBL_USER_VOLTAGE 1099
- VCCT_GXBR_USER_VOLTAGE 1100
- VCCT_GXB_USER_VOLTAGE 1101
- VCCT_L_USER_VOLTAGE 1102
- VCCT_R_USER_VOLTAGE 1103
- VCCT_USER_VOLTAGE 1104
- VCC_HPS_USER_VOLTAGE 1105
- VCC_USER_VOLTAGE 1106
- Programmer Assignments 1107
- GENERATE_CONFIG_ISC_FILE 1108
- GENERATE_CONFIG_JAM_FILE 1109
- GENERATE_CONFIG_JBC_FILE 1110
- GENERATE_CONFIG_SVF_FILE 1112
- GENERATE_ISC_FILE 1113
- GENERATE_JAM_FILE 1114
- GENERATE_JBC_FILE 1115
- GENERATE_JBC_FILE_COMPRESSED 1116
- GENERATE_SVF_FILE 1117
- HPS_EARLY_IO_RELEASE 1118
- ISP_CLAMP_STATE 1119
- ISP_CLAMP_STATE_DEFAULT 1120
- MERGE_HEX_FILE 1121
- Project-Wide Assignments 1122
- AHDL_FILE 1123
- AHDL_TEXT_DESIGN_OUTPUT_FILE 1124
- ASM_FILE 1125
- AUTO_EXPORT_VER_COMPATIBLE_DB 1126
- BASE_REVISION 1127
- BDF_FILE 1129
- BINARY_FILE 1130
- BSF_FILE 1131
- CDF_FILE 1132
- COMMAND_MACRO_FILE 1133
- CPP_FILE 1134
- CPP_INCLUDE_FILE 1135
- CUSP_FILE 1136
- CVP_REVISION 1137
- DEPENDENCY_FILE 1139
- DSPBUILDER_FILE 1140
- EDIF_FILE 1141
- ELF_FILE 1142
- ENABLE_COMPACT_REPORT_TABLE 1143
- ENABLE_REDUCED_MEMORY_MODE 1144
- EQUATION_FILE 1145
- FLOW_DISABLE_ASSEMBLER 1146
- FLOW_ENABLE_HC_COMPARE 1147
- FLOW_ENABLE_PARALLEL_MODULES 1149
- FLOW_ENABLE_POWER_ANALYZER 1150
- FLOW_ENABLE_RTL_VIEWER 1151
- GDF_FILE 1153
- HC_OUTPUT_DIR 1154
- HEX_FILE 1155
- HEX_OUTPUT_FILE 1156
- HPS_ISW_FILE 1157
- HTML_FILE 1158
- HTML_REPORT_FILE 1159
- INCLUDE_FILE 1160
- IPA_FILE 1161
- IPX_FILE 1162
- IP_COMPONENT_AUTHOR 1163
- IP_COMPONENT_DESCRIPTION 1164
- IP_COMPONENT_DISPLAY_NAME 1165
- IP_COMPONENT_GROUP 1167
- IP_COMPONENT_INTERNAL 1168
- IP_COMPONENT_NAME 1169
- IP_COMPONENT_PARAMETER 1170
- IP_COMPONENT_REPORT_HIERARCHY 1171
- IP_COMPONENT_VERSION 1172
- IP_GENERATED_DEVICE_FAMILY 1173
- IP_QSYS_MODE 1174
- IP_TARGETED_DEVICE_FAMILY 1175
- IP_TARGETED_PART_TRAIT 1176
- IP_TOOL_ENV 1177
- IP_TOOL_HIERARCHY_LEVELS 1178
- IP_TOOL_NAME 1179
- IP_TOOL_VERSION 1180
- ISC_FILE 1181
- JAM_FILE 1182
- JBC_FILE 1183
- LICENSE_FILE 1184
- LMF_FILE 1185
- LOGIC_ANALYZER_INTERFACE_FILE 1186
- MAP_FILE 1187
- MASK_REVISION 1188
- MESSAGE_DISABLE 1189
- MESSAGE_ENABLE 1190
- MIF_FILE 1191
- MISC_FILE 1193
- NUM_PARALLEL_PROCESSORS 1194
- OBJECT_FILE 1195
- OCP_FILE 1196
- PARTIAL_SRAM_OBJECT_FILE 1197
- PDC_FILE 1198
- PERSONA_FILE 1199
- PIN_FILE 1200
- POWER_INPUT_FILE 1201
- PPF_FILE 1202
- PROGRAMMER_OBJECT_FILE 1203
- PROJECT_OUTPUT_DIRECTORY 1204
- PROJECT_SHOW_ENTITY_NAME 1205
- PROJECT_USE_SIMPLIFIED_NAMES 1206
- QARLOG_FILE 1207
- QAR_FILE 1208
- QIP_FILE 1209
- QSYS_FILE 1210
- QUARTUS_PTF_FILE 1211
- QUARTUS_SBD_FILE 1212
- QUARTUS_STANDARD_DELAY_FILE 1213
- QVAR_FILE 1214
- QXP_FILE 1215
- RAW_BINARY_FILE 1216
- READ_OR_WRITE_IN_BYTE_ADDRESS 1217
- RECONFIGURABLE_REVISION 1218
- REVISION_TYPE 1219
- SBI_FILE 1222
- SDC_FILE 1223
- SDF_OUTPUT_FILE 1224
- SERIAL_BITSTREAM_FILE 1225
- SIGNALTAP_FILE 1226
- SIP_FILE 1227
- SLD_FILE 1228
- SMF_FILE 1229
- SOFTWARE_LIBRARY_FILE 1230
- SOPCINFO_FILE 1231
- SOPC_FILE 1232
- SOURCE_TCL_SCRIPT_FILE 1233
- SPD_FILE 1234
- SRAM_OBJECT_FILE 1235
- SRECORDS_FILE 1236
- SVF_FILE 1237
- SYM_FILE 1238
- SYNTHESIS_ONLY_QIP 1239
- SYSTEMVERILOG_FILE 1240
- TCL_SCRIPT_FILE 1241
- TEMPLATE_FILE 1242
- TEXT_FILE 1243
- TEXT_FORMAT_REPORT_FILE 1244
- TIMING_ANALYSIS_OUTPUT_FILE 1245
- VCD_FILE 1246
- VECTOR_TABLE_OUTPUT_FILE 1247
- VECTOR_TEXT_FILE 1248
- VECTOR_WAVEFORM_FILE 1249
- VERILOG_FILE 1250
- VERILOG_INCLUDE_FILE 1251
- VERILOG_OUTPUT_FILE 1252
- VERILOG_TEST_BENCH_FILE 1253
- VER_COMPATIBLE_DB_DIR 1254
- VHDL_FILE 1255
- VHDL_OUTPUT_FILE 1256
- VHDL_TEST_BENCH_FILE 1257
- VQM_FILE 1258
- ZIP_VECTOR_WAVEFORM_FILE 1259
- SignalProbe Assignments 1260
- SIGNALPROBE_CLOCK 1261
- SIGNALPROBE_ENABLE 1263
- SIGNALPROBE_NUM_REGISTERS 1264
- SIGNALPROBE_SOURCE 1265
- SignalTap II Assignments 1266
- ENABLE_SIGNALTAP 1267
- STP_FILE 1268
- USE_SIGNALTAP_FILE 1270
- Simulator Assignments 1271
- BREAKPOINT_STATE 1276
- CHECK_OUTPUTS 1277
- END_TIME 1278
- EXTERNAL_PIN_CONNECTION 1279
- GLITCH_DETECTION 1280
- GLITCH_INTERVAL 1281
- IMMEDIATE_ASSERTION_STATE 1285
- PASSIVE_RESISTOR 1288
- SETUP_HOLD_DETECTION 1289
- SIMULATION_COMPARE_SIGNAL 1294
- SIMULATION_COVERAGE 1296
- SIMULATION_MODE 1301
- SIMULATION_NETLIST_VIEWER 1302
- SIMULATION_VDB_RESULT_FLUSH 1304
- SIM_BEHAVIOR_SIMULATION 1328
- SIM_COMPILE_HDL_FILES 1329
- SIM_HDL_TOP_MODULE_NAME 1330
- SIM_OVERWRITE_WAVEFORM_INPUTS 1331
- SIM_TAP_REGISTER_D_Q_PORTS 1332
- START_TIME 1336
- TRIGGER_EQUATION 1337
- USER_MESSAGE 1339
- VECTOR_COMPARE_TRIGGER_MODE 1340
- VECTOR_INPUT_SOURCE 1341
- VECTOR_OUTPUT_DESTINATION 1342
- VECTOR_OUTPUT_FORMAT 1343
- X_ON_VIOLATION_OPTION 1344
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