Altera QDRII SRAM Controller MegaCore Function User Manual Page 32
- Page / 68
- Table of contents
- BOOKMARKS
- QDRII SRAM Controller 1
- MegaCore Function User Guide 1
- UG-IPQDRII-8.1 2
- Contents 3
- Additional Information 4
- 1. About This MegaCore 5
- Function 5
- Features 6
- General 6
- Description 6
- OpenCore Plus Evaluation 7
- Performance 8
- Utilization 8
- 2. Getting Started 11
- QDRII SRAM 12
- Controller 12
- Walkthrough 12
- Launch IP Toolbench 14
- Step 1: Parameterize 15
- Step 3: Set Up Simulation 17
- Step 2: Constraints 17
- Step 4: Generate 18
- Simulate the 21
- Example Design 21
- Simulate the Example Design 22
- Library Filename 23
- VHDL Gate-Level Simulations 24
- ● altera_mf_ver 25
- ● lpm_ver 25
- ● sgate_ver 25
- ● <device name>_ver 25
- ● auk_qdrii_lib 25
- Edit the PLL 28
- Compile the 29
- Compile the Example Design 30
- Program a 31
- Implement Your 31
- Set Up Licensing 31
- 3. Functional Description 33
- Control Logic 34
- Functional Description 35
- Write Data Pipeline 36
- Training Group Module 36
- Read Data Pipeline 36
- Resynchronization Logic 36
- Datapath 37
- Block Description 38
- Clock Generator 39
- Write Registers 39
- The Capture Group Module 39
- OpenCore Plus 42
- Time-Out 42
- Behavior 42
- Interfaces & 42
- Interfaces & Signals 44
- Signal Direction Description 54
- Device-Level 58
- Configuration 58
- Megawizard 60
- Parameters 61
- Parameter Value Description 62
- Board & Controller 63
- Project Settings 65
- MegaCore 66
- Verification 66
- Typographic 68
- Conventions 68
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