Altera POS-PHY Level 2 and 3 Compiler User Manual Page 12
- Page / 62
- Table of contents
- BOOKMARKS
- User Guide 1
- UG-POSPHY2_3-9.1 2
- Contents 3
- Additional Information 4
- 1. About This Compiler 5
- Features 6
- General Description 7
- OpenCore Plus Evaluation 8
- Preliminary 10
- 2. Getting Started 13
- Launch IP Toolbench 15
- Step 1: Parameterize 17
- Step 2: Set Up Simulation 21
- Step 3: Generate 22
- Simulate the Design 24
- Testbench with NativeLink 25
- Notes to table: 26
- Compile the Design 27
- Program a Device 27
- Set Up Licensing 28
- 3. Functional Description 29
- Example Configurations 30
- Example Implementations 31
- Internal Architecture 32
- POS-PHY Interface 33
- Packet Data Width Conversion 34
- Packet FIFO Buffer 34
- ‘B’ Interface 34
- Parameters 35
- Parity Settings 36
- FIFO Buffer Settings 37
- Note to Figure 3–11: 41
- Note to Figure 3–12: 42
- FIFO Buffer Size 43
- POS-PHY Level 3 Interfaces 43
- POS-PHY Level 2 Interfaces 43
- Interface Signals 44
- Global Interface 45
- POS-PHY Level 3 Interface 45
- Notes to Table 3–9: 47
- POS-PHY Level 2 Interface 50
- Notes to Table 3–11: 52
- Atlantic Interface 54
- Note to Figure 3–17: 55
- Note to Table 3–13: 57
- Signal Naming Convention 58
- MegaCore Verification 59
- 1–2 Additional Information 62
- Typographic Conventions 62
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