Altera FIR Compiler II MegaCore Function User Manual Page 15
- Page / 57
- Table of contents
- BOOKMARKS
- FIR II IP Core 1
- Contents 2
- FIR II IP Core User Guide 3
- FIR II IP Core Features 5
- Device Family Support 5
- DSP IP Core Verification 6
- About the FIR II IP Core 10
- Altera Corporation 10
- Send Feedback 10
- OpenCore Plus IP Evaluation 16
- Related Information 17
- Search for installed IP cores 18
- UG-01072 19
- 2014.12.15 19
- File Name Description 21
- Quartus II 24
- Design Flow 24
- Gate-Level Simulation 24
- RTL Simulation 24
- FIR II IP Core Parameters 26
- Parameter Value Description 27
- Coefficient Parameters 28
- Input and Output Options 29
- Signed Fractional Binary 30
- Using M-RAM Threshold 33
- Subscribe 34
- Avalon-ST Sink Interface 35
- Single Channel on Single Wire 36
- Avalon-ST Source Interface 39
- FIR II IP Core Signals 41
- Vectorized Inputs 45
- Channelization 46
- Eight Channels on Three Wires 48
- Four Channels on Four Wires 48
- Super Sample Rate 52
- Document Revision History 57
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