Altera FFT MegaCore Function User Manual download pdf (Page 3)

Block Floating Point Scaling...............................................................................4-1

Possible Exponent Values...........................................................................................................................4-2

Implementing Scaling..................................................................................................................................4-3

Example of Scaling...........................................................................................................................4-3

Unity Gain in an IFFT+FFT Pair...............................................................................................................4-5

Document Revision History................................................................................5-1

TOC-3

Altera Corporation

1 2 3 4 5 6 7 8 ... 49 50

FFT IP Core 1
Contents 2
General Description 5
Device Family Support 6
DSP IP Core Verification 6
Item Description 6
About This IP Core 10
Altera Corporation 10
Send Feedback 10
FFT IP Core Getting Started 15
Related Information 16
Search for installed IP cores 17
2014.12.15 18
File Name Description 19
Quartus II 22
Design Flow 22
Gate-Level Simulation 22
RTL Simulation 22
Fixed Transform FFTs 24
Variable Streaming FFTs 24
Input and Output Orders 25
Input Order Output 26
Mode Comments 26
FFT Processor Engines 26
Single-Output FFT Engine 27
Streaming FFT 28
Variable Streaming 30
Changing Direction 31
I/O Order 31
Buffered Burst 34
Parameter Value Description 37
Signal Name Directio 40
Component Specific Signals 42
Block Floating Point Scaling 43
Possible Exponent Values 44
Example of Scaling 45
Document Revision History 49
Date Version Changes Made 50

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Altera FFT MegaCore Function User Manual Page 3

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