Altera 10-Gbps Ethernet MAC MegaCore Function manuals

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Altera 10-Gbps Ethernet MAC MegaCore Function User Manual (175 pages)

Brand: Altera | Category: Measuring instruments | Size: 4.04 MB |

User Guide

Contents

Contents iv

Chapter 8. Registers

Chapter 9. Interface Signals

1. About This IP Core

1.2. Release Information

1.3. Device Family Support

1.4. IP Core Verification

■ Timestamping is enabled

■ ptp_1step is disabled

2.2. Design Flows

2.3.2. Simulate the IP Core

2.4.1. Specify Parameters

2.4.3. Simulate the System

[1] register bit to 1

3. 10GbE MAC Design Examples

3.2.0.2. Base Addresses

Table 3–5 on page 3–10

Creating a New 10GbE Design

3.6. 10GbE Testbenches

3.6.3. 10GbE Testbench Files

10GbE Testbenches

Notes to Table 3–6:

4.1. Software Requirements

Altera FPGA

Design Example

4.2.1. Base Addresses

Figure 4–3. Testbench

The <ip

Simulator

5.2.2. Base Addresses

1G/10GbE Design Example Files

5.5. 1G/10GbE Testbench

Testbench

1G/10GbE Testbench

5.5.4.2. Backplane-KR Mode

6.2.1. Base Addresses

ModelSim Simulator

7. Functional Description

Architecture

7.2. Interfaces

7.2.2. SDR XGMII

7.2.3. GMII

7.2.4. MII

7.3. Frame Types

7.4. Transmit Datapath

7.4.2. Address Insertion

Note to Figure 7–5:

7.4.4. XGMII Encapsulation

7.4.6. SDR XGMII Transmission

Figure 7–7. Endian Conversion

7.5. Receive Datapath

7.5.4. Address Checking

7.5.5. Frame Type Checking

7.5.6. Length Checking

7.5.7. CRC-32 and Pad Removal

7.5.8. Overflow Handling

Congestion and Flow Control

7.7.2.1. PFC Frame Reception

Figure 7–11. Fault Signaling

7.9. IEEE 1588v2

IEEE 1588v2

7.9.1. Architecture

7.9.2. Transmit Datapath

7.9.3. Receive Datapath

7.9.4. Frame Format

MAC Header

Note to Figure 7–16:

8. Registers

8.1. MAC Registers

0x0C1. Bits 4 to 31 are

0x0C3. Bits 4 to 31 are

100

Bits 4 to 31 are reserved

101

111

Name R/W Description

112

8.3. Register Initialization

113

8–20 Chapter 8: Registers

114

Chapter 8: Registers 8–21

115

8–22 Chapter 8: Registers

116

Chapter 8: Registers 8–23

117

8–24 Chapter 8: Registers

118

Chapter 8: Registers 8–25

119

9. Interface Signals

120

Note to Table 9–1:

121

Note to Figure 9–2:

123

Note to Figure 9–3:

123

Notes to Figure 9–4:

124

Note to Figure 9–5:

125

9.0.3. SDR XGMII

127

Note to Figure 9–7:

128

Note to Figure 9–8:

129

9.0.4. GMII Signals

130

9.0.5. MII Signals

130

Note to Table 9–8:

136

Note to Table 9–9:

139

1588v2 feature

142

10. Design Considerations

150

10GbE MAC XAUI/10G BASE-R PHY

151

Reconfiguration Controller

151

A. Frame Format

153

Figure A–2. VLAN Frame Format

154

A.3. Pause Frame

155

Figure A–5. PFC Frame Format

156

B. Time-of-Day (ToD) Clock

157

B.4. Parameter Setting

158

■ Bits 20 to 31: Not used

160

B.6.1. Adjusting ToD’s Drift

161

C. Packet Classifier

162

Classifier

163

D. ToD Synchronizer

166

D.2. Block Diagram

167

D.4. ToD Synchronizer Signals

169

Additional Information

171

Info–2 Additional Information

172

Document Revision History

172

Additional Information Info–3

173

How to Contact Altera

174

Typographic Conventions

174

Additional Information Info–5

175

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Altera 10-Gbps Ethernet MAC MegaCore Function manuals

Altera 10-Gbps Ethernet MAC MegaCore Function User Manual (175 pages)

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