Altera DisplayPort MegaCore Function User Manual

DisplayPort IP Core User GuideSubscribeSend FeedbackUG-011312015.05.04101 Innovation DriveSan Jose, CA 95134www.altera.com

Item DescriptionTypical Application • Interfaces within a PC or monitor• External display connections, includinginterfaces between a PC and monitor or

Figure 7-7: Reconfiguration Top Manager FSM for Arria 10 DevicesThis flow chart shows the reconfiguration FSM flow for Arria 10 transceivers. When the

Figure 7-8: RX, TX and TX Analog Reconfiguration Manager FSM for Arria 10 DevicesThis flow chart shows the reconfiguration flow for the RX, TX, and TX

DisplayPort API Reference82015.05.04UG-01131SubscribeSend FeedbackYou can use the DisplayPort IP core to instantiate sources and sinks. Source instant

The following figure shows a more detailed view of these operations. For a sink application, the userapplication must initialize the DPCD content and

Example 8-1: Typical Sink ISR Implementationbtc_dprx_aux_get_request (0,&cmd,&address,&length,data); btc_dprx_aux_handler(0,cmd,address,le

Available from ISR: YesInclude: < btc_dprx_syslib.h >Return: 0 = success, 1 = failParameters: • rx_idx—Sink instance index (0 - 3)• cmd—Pointer

Description: This function processes an AUX channel request issued by the connected DisplayPortsource.cmd and address are the command byte and the add

Description: This function transmits an AUX channel reply to the connected DisplayPort source.cmd is the reply command byte (refer to the DisplayPort

Return: 0 = success, 1 = failParameters: • rx_idx—Sink instance index (0 - 3)• wrcmd—0 = read, 1 = write• address—Address• length—Length (1 - 255)• da

btc_dprx_hpd_getPrototype: int btc_dprx_hpd_get(BYTE rx_idx)Thread-safe: YesAvailable from ISR: YesInclude:<btc_dprx_syslib.h>Return: 0 = succes

About This IP Core22015.05.04UG-01131SubscribeSend FeedbackThis document describes the Altera® DisplayPort MegaCore® function, which provides support

Related Information• btc_dprx_hpd_get on page 8-8• btc_dprx_hpd_set on page 8-9btc_dprx_hpd_setPrototype:void btc_dprx_hpd_set( BYTE rx_idx, int

Return: 0 = success, 1 = failParameters: • rx_idx—Sink instance index (0 - 3)• rx_base_addr—RX base address• rx_irq_id—RX IRQ ID• rx_irq_num—RX IRQ nu

btc_dprx_syslib_initPrototype: int btc_dprx_syslib_init(void)Thread-safe: NoAvailable from ISR: NoInclude: < btc_dprx_syslib.h >Return: 0 = succ

btc_dptx_syslib API ReferenceThis section provides information about the DisplayPort source system library functions(btc_dptx_syslib), including:• C p

btc_dptx_aux_i2c_writePrototype:int btc_dptx_aux_i2c_write( BYTE address, BYTE size, BYTE *data, BYTE mot)Thread-safe: NoAvailable

Return: • 0 = AUX_ACK replied• 1 = Source internal error• 2 = Reply timeout• 3 = AUX_NACK replied• 4 = AUX_DEFER replied• 5 = Invalid replyParameters

Related Informationbtc_dptx_aux_read on page 8-13btc_dptx_baseaddrPrototype: unsigned int btc_dptx_baseaddr(void)Thread-safe: YesAvailable from ISR: Y

Related Informationbtc_dptx_edid_read on page 8-16btc_dptx_edid_readPrototype: int btc_dptx_edid_read(BYTE *data)Thread-safe: NoAvailable from ISR: Ye

Parameters: • link_rate—Link rate (Gbps): 0 = 1.62; 1 = 2.70; 2 = 5.40• lane_count—1, 2, or 4• volt_swing—0, 1, 2, or 3• pre_emph—0, 1, 2, or 3• new_c

btc_dptx_set_color_spacePrototype:int btc_dptx_set_color_space( BYTE format, BYTE bpc, BYTE range, BYTE colorimetry)Thread-safe: NoAv

Device Family SupportThe following table lists the link rate support offered by the DisplayPort IP core for each Altera devicefamily.Table 2-1: Link R

Description: Initializes the system library. Should be invoked as the first function in the libraryby main( ). Set the base address of TX or RX to BTC

Description: This function handles test automation requests from the connected DisplayPortsink. You should invoke this function after the IP core sens

DisplayPort Source Register Map and DPCDLocations92015.05.04UG-01131SubscribeSend FeedbackDisplayPort source instantiations require an embedded contro

Reset: 0×00000000Table 9-2: DPTX_TX_CONTROL BitsBit Bit Name Function31HPD_IRQ_ENEnables an IRQ issued to the Nios II processor on an HPD event:• 0 =

Bit Bit Name Function3:0TPCurrent training pattern:• 0000 = Normal video• 0001 = Training pattern 1• 0010 = Training pattern 2• 0011 = Training patter

Source MSA RegistersThe MSA registers are allocated at addresses:• 0×0020 through 0×002e for Stream 0• 0×0040 through 0×004e for Stream 1• 0×0060 thro

Table 9-6: DPTX0_MSA_HTOTAL BitsBit Bit Name Function31:16 Unused15:0 HTOTAL Main stream attribute HTOTALDPTX0_MSA_VTOTALAddress: 0×0023Direction: ROR

Table 9-9: DPTX0_MSA_HSW BitsBit Bit Name Function31:15 Unused14:0 HSW Main stream attribute horizontalsync widthDPTX0_MSA_HSTARTAddress: 0×0026Direct

Table 9-12: DPTX0_MSA_VSP BitsBit Bit Name Function31:1 Unused0 VSP Main stream attribute verticalsync polarity• 0 = Positive• 1 = NegativeDPTX0_MSA_V

Table 9-15: DPTX0_MSA_VHEIGHT BitsBit Bit Name Function31:16 Unused15:0 VHEIGHT Main stream attributeVHEIGHTDPTX0_MSA_MISC0Address: 0×002cDirection: R

Table 2-2: DisplayPort IP Core FPGA Resource Utilization The table below shows the resource information for Arria V and Cyclone V devices using M10K;

Table 9-18: DPTX0_MSA_MISC1 BitsBit Bit Name Function31:7 Unused6 COLORIMETRY 0 = ITU-R BT601-51 = ITU-R BT709-55 DYNAMIC_RANGE 0 = VESA (from 0 to ma

DPTX_PRE_VOLT1These ports drive the respective tx_analog_reconfig ports.Address: 0×0011Direction: RWReset: 0×00000000Table 9-20: DPTX_PRE_VOLT1 BitsBi

Table 9-22: DPTX_PRE_VOLT3 BitsBit Bit Name Function31:4 Unused3:2PRE3Pre-emphasis output on lane 31:0VOLT3Voltage swing output on lane 3DPTX_RECONFIG

Table 9-24: DPTX_TIMESTAMP BitsBit Bit Name Function31:24 Unused 8’b0000000023:0TIMESTAMPFree-running counter value (1 tick equals 100 µs)Source Audio

Bit Bit Name Function2:0CH_COUNTChannel count• 000 = 1 channel• 001 = 2 channels...• 111 = 8 channelsSource CRC RegistersThe CRC registers are allocat

Bit Bit Name Function15:0CRC_GInput video CRC for the greencomponentComputed video CRC blue component, DPTX0_CRC_B, bits.Address: 0×0032Direction: ROR

Bit Bit Name Function0 MST_ENEnable or disable MST• 1 = MST framing• 0 = SST framingWhen you assert VCPTAB_UPD_FORCE, the source forces the VC payload

Table 9-31: DPTX_MST_VCPTAB1 BitsBit Bit Name Function31:28 VCPSLOT15VC payload ID or slot 1527:24 VCPSLOT14VC payload ID or slot 1423:20 VCPSLOT13VC

DPTX_MST_VCPTAB3VC Payload ID TableAddress: 0×00a5Direction: RWReset: 0×00000000Table 9-33: DPTX_MST_VCPTAB3 BitsBit Bit Name Function31:28 VCPSLOT31V

Bit Bit Name Function11:8 VCPSLOT34VC payload ID or slot 347:4 VCPSLOT33VC payload ID or slot 333:0 VCPSLOT32VC payload ID or slot 32DPTX_MST_VCPTAB5V

Getting Started32015.05.04UG-01131SubscribeSend FeedbackThis chapter provides a general overview of the Altera IP core design flow to help you quickly

Table 9-36: DPTX_MST_VCPTAB6 BitsBit Bit Name Function31:28 VCPSLOT55VC payload ID or slot 5527:24 VCPSLOT54VC payload ID or slot 5423:20 VCPSLOT53VC

DPTX_MST_TAVG_TSTarget Average TimeslotsAddress: 0×00aaDirection: RWReset: 0×40404040Table 9-38: DPTX_MST_TAVG_TS BitsBit Bit Name Function31 Unused30

For transaction replies:1. Issue a transaction request.2. Wait for MSG_READY to be 1. Implement a timeout.3. Read the transaction reply’s total length

DPTX_AUX_BYTE0AUX Transaction Byte 0 Register.Address: 0×0102Direction: RWReset: 0×00000000Table 9-41: DPTX_AUX_BYTE0 BitsBit Bit Name Function31:8 Un

Bit Bit Name Function7:0BYTETransaction length[3:0] for the next request, or data(2) receivedin the last reply (refer to the DisplayPort specification

Table 9-46: DPTX_AUX_BYTE5 BitsBit Bit Name Function31:8 Unused7:0BYTETransaction data(2) for the next request, or data(5) receivedin the last replyDP

Reset: 0×00000000Table 9-49: DPTX_AUX_BYTE8 BitsBit Bit Name Function31:8 Unused7:0 BYTE Transaction data(5) for the next request, or data(8) received

Direction: RWReset: 0×00000000Table 9-52: DPTX_AUX_BYTE11 BitsBit Bit Name Function31:8 Unused7:0BYTETransaction data(8) for the next request, or data

DPTX_AUX_BYTE14AUX Transaction Byte 14 Register.Address: 0×0110Direction: RWReset: 0×00000000Table 9-55: DPTX_AUX_BYTE14 BitsBit Bit Name Function31:8

DPTX_AUX_BYTE17AUX Transaction Byte 17 Register.Address: 0×0113Direction: RWReset: 0×00000000Table 9-58: DPTX_AUX_BYTE17 BitsBit Bit Name Function31:8

• Simulate the behavior of a licensed IP core in your system.• Verify the functionality, size, and speed of the IP core quickly and easily.• Generate

Source-Supported DPCD LocationsThe following table describes the DPCD locations (or location groups) that are supported in DisplayPortsource instantia

Location Name AddressPAYLOAD_ALLOCATE_START_TIME_SLOT 0×01C1PAYLOAD_ALLOCATE_TIME_SLOT_COUNT 0×01C2SINK_COUNT 0×0200DEVICE_SERVICE_IRQ_VECTOR 0×0201LA

DisplayPort Sink Register Map and DPCDLocations102015.05.04UG-01131SubscribeSend FeedbackDisplayPort sink instantiations greatly benefit from and may

Table 10-2: DPRX_RX_CONTROL BitsBit Bit Name Function31:30 Unused29LQA_ACTIVE• 0 = Link Quality Analysis not used• 1 = Link Quality Analysis in progre

Table 10-3: DPRX_RX_CONTROL Bits (Non-Controller Mode)Bit Bit Name Function31:24 Unused23:16RX_LINK_RATEMain link rate expressed as multiples of 270 M

Bit Bit Name Function6SYM_LOCK20 = Symbol unlocked (lane 2)1 = Symbol locked (lane 2)5SYM_LOCK10 = Symbol unlocked (lane 1)1 = Symbol locked (lane 1)4

Bit Bit Name Function5SYM_LOCK10 = Symbol unlocked (lane 1)1 = Symbol locked (lane 1)4SYM_LOCK00 = Symbol unlocked (lane 0)1 = Symbol locked (lane 0)3

Bit Bit Name Function23Unused22:21 PHY_SINK_TEST_LANE_SELSpecifies the lane that is being tested, when PHY_SINK_TEST_LANE_EN is 1,• 00 = Lane 0• 01 =

Bit Bit Name Function1:0CNTSELCount selection:• 00 = Disparity and illegal comma codes• 01 = Disparity• 10 = Illegal comma codes• 11 = ReservedDPRX_BE

Reset: 0×00000000Table 10-8: DPRX_BER_CNTI0 BitsBit Bit Name Function31 Unused30:16CNT1Symbol error counter for lane 115 Unused14:0CNT0Symbol error co

Related InformationDisplayPort IP Core Simulation Example on page 7-1The Altera DisplayPort simulation example allows you to evaluate the functionalit

DPRX0_MSA_MVIDAddress: 0×0020Direction: ROReset: 0×00000000Table 10-10: DPRX0_MSA_MVID BitsBit Bit Name Function31:24 Unused23:0MVIDMain stream attrib

Reset: 0×00000000Table 10-13: DPRX0_MSA_VTOTAL BitsBit Bit Name Function31:16 Unused15:0MVIDMain stream attribute VTOTALDPRX0_MSA_HSPMSA horizontal sy

Reset: 0×00000000Table 10-16: DPRX0_MSA_HSTART BitsBit Bit Name Function31:16 Unused15:0HSTARTMain stream attribute HSTARTDPRX0_MSA_VSTARTAddress: 0×0

Direction: ROReset: 0×00000000Table 10-19: DPRX0_MSA_VSW BitsBit Bit Name Function31:15 Unused14:0VSWMain stream attribute vertical synchronization wi

Table 10-22: DPRX0_MSA_MISC0 BitsBit Bit Name Function31:8 Unused7:0MISC0Main stream attribute MISC0DPRX0_MSA_MISC1Address: 0×002dDirection: ROReset:

Sink Audio RegistersThe audio registers are allocated at addresses:• 0×0030 through 0×003f for Stream 0• 0×0050 through 0×005f for Stream 1• 0×0070 th

Reset: 0×00000000Table 10-27: DPRX0_AUD_AIF0 BitsBit Bit Name Function31:8 Unused7:0AIFReceived audio InfoFrame byte 0 (refer to CEA-861-Especificatio

Direction: ROReset: 0×00000000Table 10-30: DPRX0_AUD_AIF3 BitsBit Bit Name Function31:8 Unused7:0AIFReceived audio InfoFrame byte 3 (refer to CEA-861-

Bit Bit Name Function29:20 Unused19:16 VCP_ID3VC payload ID for Stream 315:12 VCP_ID2VC payload ID for Stream 211:8 VCP_ID1VC payload ID for Stream 17

Address: 0×00a2Direction: RWReset: 0×00000000Table 10-34: DPRX_MST_VCPTAB0 BitsBit Bit Name Function31:28 VCPSLOT7VC payload ID or slot 727:24 VCPSLOT

DisplayPort Source42015.05.04UG-01131SubscribeSend FeedbackSource OverviewThe DisplayPort source has a scalable main link with 1, 2, or 4 lanes for a

Bit Bit Name Function3:0 VCPSLOT8VC payload ID or slot 8DPRX_MST_VCPTAB2VC Payload ID TableAddress: 0×00a4Direction: RWReset: 0×00000000Table 10-36: D

Bit Bit Name Function23:20 VCPSLOT29VC payload ID or slot 2919:16 VCPSLOT28VC payload ID or slot 2815:12 VCPSLOT27VC payload ID or slot 2711:8 VCPSLOT

Reset: 0×00000000Table 10-39: DPRX_MST_VCPTAB5 BitsBit Bit Name Function31:28 VCPSLOT47VC payload ID or slot 4727:24 VCPSLOT46VC payload ID or slot 46

DPRX_MST_VCPTAB7VC Payload ID TableAddress: 0×00a9Direction: RWReset: 0×00000000Table 10-41: DPRX_MST_VCPTAB7 BitsBit Bit Name Function31:28 VCPSLOT63

The sink asserts the IRQ when AUX_IRQ_EN = 1 and MSG_READY = 1. To deassert IRQ, set AUX_IRQ_EN to 0or read from DPRX_AUX_COMMAND.Address: 0×0100Direc

Bit Bit Name Function30READY_TO_TX0 = Busy sending a reply or waiting for a request1 = Ready to send a reply29:2Unused1SRC_PWR_DETECT0 = Upstream powe

Bit Bit Name Function7:0BYTETransaction address[15:8] received in the last request, or data(0)for the next replyDPRX_AUX_BYTE1AUX Transaction Byte 1 R

Table 10-48: DPRX_AUX_BYTE3 BitsBit Bit Name Function31:8 Unused7:0BYTETransaction data(0) received in the last request, or data(3) for thenext replyD

Reset: 0×00000000Table 10-51: DPRX_AUX_BYTE6 BitsBit Bit Name Function31:8 Unused7:0BYTETransaction data(3) received in the last request, or data(6) f

Direction: RWReset: 0×00000000Table 10-54: DPRX_AUX_BYTE9 BitsBit Bit Name Function31:8 Unused7:0BYTETransaction data(6) received in the last request,

Source Functional DescriptionThe DisplayPort source has a complete set of parameters for optimizing device resources.The DisplayPort source consists o

DPRX_AUX_BYTE12AUX Transaction Byte 12 Register.Address: 0×010fDirection: RWReset: 0×00000000Table 10-57: DPRX_AUX_BYTE12 BitsBit Bit Name Function31:

Bit Bit Name Function7:0BYTETransaction data(11) received in the last request, or data(14)for the next replyDPRX_AUX_BYTE15AUX Transaction Byte 15 Reg

Table 10-62: DPRX_AUX_BYTE17 BitsBit Bit Name Function31:8 Unused7:0BYTETransaction data(14) received in the last requestDPRX_AUX_BYTE18AUX Transactio

Address: 0×0117WO0×00000000Table 10-65: DPRX_AUX_I2C1 BitsBit Bit Name Function31:15 Unused14:8END_ADDRI2C slave end address7 Unused6:0START_ADDRI2C s

Bit Bit Name Function12HPD_IRQWriting this bit at 1 generates a 0.75-ms long HPD IRQ (low pulse).This bit is WO.To use this bit, HPD_EN must be 1.11HP

Location Name Address WithoutControllerWith ControllerEDP_CONFIGURATION_CAP0×000D — YesTRAINING_AUX_RD_INTERVAL0×000E — YesADAPTER_CAP0×000F — YesFAUX

Location Name Address WithoutControllerWith ControllerTRAINING_LANE0_1_SET20×010F — YesTRAINING_LANE2_3_SET20×0110 — YesMSTM_CTRL0×0111 — YesAUDIO_DEL

Location Name Address WithoutControllerWith ControllerTEST_REQUEST 0×0218— YesTEST_LINK_RATE 0×0219— YesTEST_LANE_COUNT0×0220 — YesTEST_PATTERN0×0221

Location Name Address WithoutControllerWith ControllerTEST_CRC_R_Cr0×0240 Yes —TEST_CRC_G_Y0×0242 Yes —TEST_CRC_B_Cb0×0244 Yes —TEST_SINK_MISC0×0246 Y

Location Name Address WithoutControllerWith ControllerIEEE_OUI0×0401 — YesIEEE_OUI0×0402 — YesDEVICE_IDENTIFICATION_STRING0×0403 — YesHARDWARE_REVISIO

Figure 4-3: DisplayPort Source Functional Block Diagram8B/10BEncoderMultiplexerFixed MSA(txN_msa)Avalon-MM(tx_mgmt)Bidirectional AUX DataAUX Debug Str

Location Name Address WithoutControllerWith ControllerLANE2_3_STATUS_ESI0×200D — YesLANE_ALIGN STATUS_UPDATED_ESI0×200E — YesSINK_STATUS_ESI0×200F — Y

Additional InformationA2015.05.04UG-01131SubscribeSend FeedbackDocument Revision HistoryThe following table lists the revision history for this docume

Date Version ChangesDecember 2014 2014.12.15• Added information about multi-stream support (MST, 1 to 4 sourceand sink streams). You can access this f

Date Version Changes• Changed the value of the following source register bits:• 0×0000 - Bits RX_LINK_RATE• 0×0001 - Bits RX_LINK_RATE• 0×0002 - Bits

Date Version ChangesJune 2014 2014.06.30• Native PHY is removed from the IP core; included informationabout how to instantiate the PHY outside the Dis

Date Version ChangesNovember 2013 13.1 • Updated the source and sink register map information.• Added dual and quad pixel mode support.• Added support

ContentsDisplayPort IP Core Quick Reference... 1-1About This IP Core...

Packetizer PathThe packetizer path provides video data resampling and packetization, and consists of the following steps:1. The pixel steer block deci

Embedded DisplayPort (eDP) SupportThe DisplayPort IP core is compliant with eDP version 1.3. eDP is based on the VESA DisplayPortstandard. It has the

Parameter DescriptionPixel input mode Select the number of pixels per clock (single, dual, orquad symbol).• If you select dual pixels per clock, the p

Parameter Description16-bpc YCbCr 4:2:2 (32 bpp) Turn on to support 32 bpp encoding.Support MST Turn on to enable multi-stream support.Max stream coun

Table 4-3: Transceiver Management Interfacen is the number of TX lanes.Interface Port Type Clock Domain Port Direction Descriptionxcvr_mgmt_clkClock N

Table 4-4: Video Interfacev is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad). N is the streamnumber; fo

Table 4-6: Secondary InterfaceN is the stream number; for example, tx_msa_conduit represents Stream 0, tx1_msa_conduit represents Stream1, and

Table 4-8: TX Transceiver Interfacen is the number of TX lanes, s is the number of symbols per clock.Note: Connect the DisplayPort signals to the Nati

AUX InterfaceThe IP core has three ports that control the serial data across the AUX channel:• Data input (tx_aux_in)• Data output (tx_aux_out)• Outpu

Figure 4-4: Video Input Data Format18 bpp to 48 bpp port width when txN_video_in port width is 48 (16 bpc, 1 pixel per clock)47 32 31 16 15 0txN_vid_d

Controller Interface...5-13AUX Int

reset (tx_digitalreset), analog reset (tx_analogreset), and PLL powerdown signals(tx_pll_powerdown) of the transceiver.Transceiver Reconfiguration Int

The txN_ss interface input data format corresponds to four, 15-nibble code words as specified by theDisplayPort version 1.2a specification section 2.2

Figure 4-8: Typical Secondary Stream Packet000HB2000HB3000HB1000DB15DB10DB9DB8DB7DB14DB13DB12DB11DB6DB5DB4DB3DB2DB1HB0 DB0DB31DB26DB25DB24DB23DB30DB29

Table 4-10: Audio SignalsSignal CommentstxN_audio_clkAudio interface input clock.txN_audio_validAudio input data valid.txN_audio_muteWhen asserted, in

Bit Name Bit Position DescriptionSP Byte 3, bit 7 Sample present bit:1: Sample information is present and can be processed.0: Sample information is no

Bit Signal Comments79:64Vstart[15:0] Vertical active start from V-sync start in lines (V-sync width +Vertical back porch)63VSP V-sync polarity 0 = Act

Figure 4-10: Source Clock TreeFront-EndAudio FIFOAudioEncoderSecondaryStreamEncoderFront-EndVideo FIFOAUXControllerControllerInterfaceSyncBack-EndEnco

DisplayPort Sink52015.05.04UG-01131SubscribeSend FeedbackSink OverviewThe DisplayPort sink has a scalable main link with 1, 2, or 4 lanes for a total

Figure 5-2: DisplayPort Sink Top-Level Block DiagramDisplayPort SinkDecoderrxN_ssrxN_ss_clkrxN_audiorxN_video_outrxN_vid_clkrxN_msa_conduitrxN_streamr

Figure 5-3: DisplayPort Sink Functional Block DiagramVideo Output(rxN_video_out)20-Bit (Dual Symbol) or 40-Bit (Quad Symbol) Data from Transceiver(rx_

btc_dptx_syslib API Reference... 8-12btc_

Embedded DisplayPort (eDP) SupportThe DisplayPort IP core is compliant with eDP version 1.3. eDP is based on the VESA DisplayPortstandard. It has the

Parameter DescriptionPixel output mode Select the number of pixels per clock (single, dual, orquad symbol).• If you select dual pixels per clock, the

Parameter Description16-bpc RGB or YCbCr 4:4:4 (48 bpp) Turn on to support 48 bpp decoding.8-bpc YCbCr 4:2:2 (16 bpp) Turn on to support 16 bpp decodi

Interface Port Type Clock Domain Port Direction Descriptionrx_mgmt AV-MM clkrx_mgmt_address[8:0]InputAvalon-MM interfacefor embeddedcontrollerrx_mgmt_

Table 5-4: Video Interfacev is the number of bits per color, p is the pixels per clock (1 = single, 2 = dual, and 4 = quad), and N is the streamnumber

Interface Port Type Clock Domain Port Direction Descriptionrx_aux Conduit aux_clkrx_aux_inInputAUX channel interfacerx_aux_outOutputrx_aux_oeOutputrx_

Interface Port Type Clock Domain Port Direction DescriptionEDID(rx_edid)AV-MM aux_clkrx_edid_address[7:0]OutputAvalon-MM masterinterface to externalon

Interface Signal Type Clock Domain Port Direction DescriptionMSA(rxN_msa_conduit)Conduitrx_ss_clk rxN_msa[216:0]Output Output for currentMSA parameter

Table 5-9: RX Transceiver Interfacen is the number of RX lanes, s is the number of symbols per clock.Note: Connect the DisplayPort signals to the Nati

Controller InterfaceThe controller interface allows you to control the sink from an external or on-chip controller, such as theNios II processor for d

DPTX_MST_VCPTAB0...9-15DPTX_MST_VCPTAB1...

Port Commentsrx_aux_debug_eopIndicates the message packet’s last byte. The last byte should be ignoredand is not part of the message.rx_aux_debug_errI

Bit Comments39:32 Lane 2 symbol n31:24 Lane 1 symbol n + 123:16 Lane 1 symbol n15:8 Lane 0 symbol n + 17:0 Lane 0 symbol n Table 5-12: rxN_stream_dat

Bit Comments7:0 Lane 0 symbol nWhen data is received, data is produced on lane 0, lanes 0 and 1, or on all four lanes according to howmany lanes are c

Figure 5-5: Video Output Data Format18 bpp to 48 bpp Port Width when rxN_video_out port width is 48 (16 bpc, 1 Pixel per Clock)47 32 31 16 15 0rxN_vid

Clocked Video Input InterfaceThe rxN_video_out interface may interface with a clocked video input (CVI). CVI accepts the followingvideo signals with a

assign vid_h_sync = rx_vid_h_sync;assign vid_de = rx_vid_valid;assign vid_v_sync = rx_vid_v_sync;RX Transceiver InterfaceThe transceiver or Native PHY

downstream Reed-Solomon decoder. The format differs for both header and payload, as shown in thefollowing figure.Figure 5-8: rxN_ss Input Data Format0

Figure 5-9: Typical Secondary Stream Packet000HB2000HB3000HB1000DB15DB10DB9DB8DB7DB14DB13DB12DB11DB6DB5DB4DB3DB2DB1HB0 DB0DB31DB26DB25DB24DB23DB30DB29

Figure 5-10: rxN_audio Data OutputAudio Sample PeriodrxN_audio_lpcm_datarx_ss_clkrxN_audio_validThe captured audio infoframe is available on the audio

Bit Signal Comments214:209vbid_vbid[5:0]VB-ID bit field:• vbid[0] - VerticalBlanking_Flag• vbid[1] - FieldID_Flag (for progressive video, this remains

DPRX0_MSA_HTOTAL...10-9DPRX0_MSA_VTOTAL...

Bit Signal Comments15:8msa_MISC0[7:0] The MISC0[7:1] and MISC1[7] fields indicate the colorencoding format. The color depth is indicated in MISC0[7:5]

Figure 5-11: Sink Clock TreeAudioDecoderBack-EndVideo FIFOAUXControllerControllerInterfaceDCFIFOFront-EndDecoderDCFIFODCFIFODCFIFOHSSIO0HSSIO1HSSIO2HS

DisplayPort IP Core Hardware Demonstration62015.05.04UG-01131SubscribeSend FeedbackThe Altera DisplayPort hardware demonstration evaluates the functio

Figure 6-1: Hardware Demonstration OverviewDisplayPort IP Core(Source)ClockRecoveryDisplayPort IP Core (Sink)User LEDsRXTXBitec HSMCDisplayPortDaughte

Figure 6-2: Hardware Demonstration Block DiagramNios IIProcessorTransceiverReconfigurationRXTXDisplayPort IP Core BitecDisplayPort CoreQsys System (co

Arria V/Cyclone V/Stratix V/ FunctionUSER_LED[7:6]These LEDs indicate the RX link rate.• 00 = RBR• 01 = HBR• 10 = HBR2Tip: When creating your own desi

The clock recovery core produces resynchronized video data together with the following clocks:• Recovered video pixel clock• Second clock with twice t

Table 6-2: Clock Recovery Core ParametersParameter Default Value DescriptionSYMBOLS_PER_CLOCK 4 Specifies the configuration of the DisplayPortRX trans

Table 6-3: Clock Recovery Interface SignalsInterface Port Type Clock Domain Port Direction Descriptioncontrol clock Clock N/A clk Input Control logic

Interface Port Type Clock Domain Port Direction DescriptionRX link rate Conduitasynchronousrx_link_rate[1:0]Input DisplayPort RX link rate.• 00 = RBR

DPRX_AUX_BYTE15...10-30DPRX_AUX_BYTE16..

Interface Port Type Clock Domain Port Direction DescriptionVideo Input Conduit vidin_clkvidin_clkInput Pixel clock.vidin_data(BPP*PIXELS_PER_CLOCK–1:0

Interface Port Type Clock Domain Port Direction DescriptionVideo Output Conduit rec_clkrec_clk Output Reconstructed videoclock.rec_clk_x2 Output Recon

Figure 6-5: Video Input Port Timing Diagramvidin_datavidin_validvidin_solvidin_eolvidin_sofvidin_oefWhen the PIXELS_PER_CLOCK parameter is greater tha

Parameters Single Reference Clock SettingsDatapath OptionsEnable standard PCSOnNumber of data channels1, 2 or 4Note: If you select 1 or 2, you mustins

TX PLL0Selected reference clock source0Selected clock network×1 or ×NNote: If you select ×1, you must instantiatethe PHY instance multiple times foral

Required HardwareThe hardware demonstration requires the following hardware:• Altera FPGA kit (includes USB cable to connect the board to your PC); th

Figure 6-7: HSMC Connector Schematic DiagramFigure 6-8: TI Redriver to DisplayPort Source Connector Schematic DiagramUG-011312015.05.04Required Hardwa

Figure 6-9: DisplayPort Sink Connector to TI Redriver Schematic DiagramTable 6-5: Bitec DisplayPort Daughter Card SignalsThe following table describes

Bitec DP Card Signal Bitec Card I/ODescriptionHSMC Connector J4AHSMA_RX_P[3..0], HSMA_RX_N[3..0] OutputRX Main Link lane[3..0] differential signals.Th

HSMC Connector J4BRX_SENSE_N OutputThe sink uses this to detect the source power.• 0=Source DisplayPort cable is not powered.• 1=Source DisplayPort ca

DisplayPort IP Core Quick Reference12015.05.04UG-01131SubscribeSend FeedbackThis document describes the Altera® DisplayPort MegaCore®function, which p

HSMC Connector J4BAUX_RX_DRV_OUT InputRX AUX channel output.Use this signal if the external AUX driver/receiver(U3) is populated.TX_CAD, RX_SDA_DDC, R

DP RX Connector J1PWR_OUT OutputDP_PWR 3.3V @ 500mA for sink-side cable adapter.A standard DisplayPort cable must have no wire forthis pin.DP RX Conne

//*********************************************************// Program VOD Level 1 and Pre-emphasis Level 0 for lane 1// (DPCD addr=0×00104, data=0×01)

Example 6-2: Example Hardware SetupFigure 6-10: Example Hardware Setup Using FPGA Development Board, Bitec Daughter Card,and Cables.Related Informatio

Set Up the HardwareSet up the hardware using the following steps:1. Connect the Bitec daughter card to the FPGA development board.2. Connect the devel

Table 6-6: Hardware Demonstration FilesFiles are named with <prefix>_<name>.<extension> where <prefix> represents the device (

File Type File DescriptionQuartus II IPfilesbitec_reconfig_alt_<prefix>.qipbitec_clkrec_dist.qipbitec_clkrec.qipQuartus II IP files that list th

Note: To find <USB cable number>, use the jtagconfig command.Note: Refer to the Nios II Software Build Tools Reference chapter in the Nios II So

Figure 6-12: MSA OutputThe Nios II AUX printout shows each message packet on a separate line.• The first field is the incremental timestamp in microse

DisplayPort IP Core Simulation Example72015.05.04UG-01131SubscribeSend FeedbackThe Altera DisplayPort simulation example allows you to evaluate the fu

Item DescriptionIP Core InformationCore Features• Conforms to the Video ElectronicsStandards Association (VESA) specifica‐tion version 1.2a• Scalable

Figure 7-1: Simulation Example Block Diagram for Arria 10 DevicesDisplayPort IP Core(a10_dp.qsys)Native PHY IP Core(gxb_tx.qsys)Transceiver PHY ResetC

Figure 7-2: Simulation Example Block Diagram for Arria V and Stratix V DevicesThe files are named <prefix>_<name>.<extension> where

Table 7-1: Simulation Example Files for Arria 10 DevicesFile Type File DescriptionSystem VerilogHDL designfilesa10_dp_harness.sv Top-level test harnes

File Type File DescriptionWaveform .dofilesall.do Waveform that shows a combination of all waveforms.reconfig.do Waveform that shows the signals invol

File Type File Descriptionvga_driver.v VGA driver (generates a test image).IP Catalog files<prefix>_ dp.v IP Catalog variant for the DisplayPort

This script executes the following commands:• Generate the simulation files for the DisplayPort, transceivers, and transceiver reconfiguration IPcores

View the ResultsYou can view the results in the ModelSim GUI by loading various .do files in the Wave viewer.1. Launch the ModelSim GUI with the vsim

Figure 7-4: TX Reconfiguration WaveformIn the timing diagram below, tx_link_rate is set to 1 (HBR). When the core makes a request, thetx_reconfig_req

Figure 7-5: TX Analog Reconfiguration WaveformIn the timing diagram below, tx_vod and tx_emp are both set to 00. When the core makes a request,the tx_

Figure 7-6: RX Video WaveformThis timing diagram shows an example RX video waveform when interfacing to CVI. The rx_vid_eolsignal generates the h_sync