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Cyclone III Development Board
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Altera Cyclone III Development Board User Manual Page 80
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Info–4
Addit
i
onal Infor
mati
on
Ty
pogra
phi
c
C
onv
entions
Cycl
one III 3C
120 D
e
vel
opm
ent
Boar
d R
ef
er
enc
e M
anual
© March 2009
Altera Corporation
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Reference Manual
1
MNL-01029-1.4
2
Contents
3
Additional Information
4
1. Overview
5
Board Component Blocks
6
Chapter 1: Overview 1–3
7
General Description
7
Block Diagram
8
1–6 Chapter 1: Overview
10
Handling the Board
10
2. Board Components
11
Board Overview
12
Featured FPGA (U20)
14
I/O and Clocking Resources
15
MAX II CPLD
16
Note to Table 2–5:
24
Configuration
25
Notes to Table 2–7:
26
Status Elements
27
Setup Elements
28
JTAG Control DIP Switch
29
POWER SELECT Rotary Switch
31
Note to Table 2–16:
32
Clocking Circuitry
33
Oscillators
35
General User Interfaces
36
User-Defined DIP Switches
37
User-Defined LEDs
37
HSMC User-Defined LEDs
38
DDR2 User-Defined LEDs
39
7-Segment Displays
40
LCD Information
41
Character LCD (J4)
42
Graphics LCD (J13)
43
Note to Table 2–39:
44
CPLD using the FSM bus
45
Note to Table 2–41:
47
USB 2.0 MAC/PHY
48
Note to Table 2–42:
49
10/100/1000 Ethernet
50
HSMC host
55
On-Board Memory
58
Flash Memory
68
Note to Table 2–56:
69
70
Power Supply
72
Power Measurement
74
Notes to Table 2–62:
75
Note to Table:
78
Additional Information Info–3
79
Typographic Conventions
79
Info–4 Additional Information
80
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